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VLSI Implementation of a High-Speed Iterative Sorted MMSE QR Decomposition

P. Luethi, A. Burg, S. Haene, D. Perels, N. Felber, W. Fichtner
2007 2007 IEEE International Symposium on Circuits and Systems  
This paper describes the architecture and results of the first VLSI implementation of an iterative sorted QR decomposition preprocessor for MIMO receivers.  ...  The presented architecture performs MIMO channel preprocessing using Givens rotations in order to compute the minimum mean squared error QR decomposition.  ...  The described VLSI architecture incorporates optimized fixed-point arithmetic and shows how a combination of CORDIC circuits and complex-valued multipliers allows to achieve a very high throughput with  ... 
doi:10.1109/iscas.2007.378495 dblp:conf/iscas/LuethiBHPFF07 fatcat:7t6hha7hi5dczahu7slqglbuqi

Gram-Schmidt-based QR decomposition for MIMO detection: VLSI implementation and comparison

P. Luethi, C. Studer, S. Duetsch, E. Zgraggen, H. Kaeslin, N. Felber, W. Fichtner
2008 APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems  
The QR decomposition (QRD) is an important prerequisite for many different detection algorithms in multipleinput multiple-output (MIMO) wireless communication systems.  ...  In order to ensure a fair comparison, both QRD circuits have been integrated in the same IC manufacturing technology, with equal functionality, and the same numeric precision.  ...  Throughput Optimizations For high-throughput VLSI architectures, an important design aspect is the limitation in memory bandwidth.  ... 
doi:10.1109/apccas.2008.4746151 dblp:conf/apccas/LuethiSDZKFF08 fatcat:jmyxujs46ndyzow7t4h347xqia

Interpolation-Based QR Decomposition and Channel Estimation Processor for MIMO-OFDM System

Po-Lin Chiu, Lin-Zheng Huang, Li-Wei Chai, Yuan-Hao Huang
2011 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
possesses a scalable property to save the power consumption for interpolation-based QR decomposition in the variable-rank MIMO scheme.  ...  The processor supports 2 2, 2 4 and 4 4 QR-based MIMO detection for the 3GPP-LTE MIMO-OFDM system and achieves the throughput of 35.16 MQRD/s at its maximum clock rate 140.65 MHz.  ...  ACKNOWLEDGMENT The authors would like to thank Chip Implementation Center of National Applied Research Laboratories in Taiwan for technical support.  ... 
doi:10.1109/tcsi.2010.2092090 fatcat:3akjllo2dngq3eto2woh7bmus4

Parallel Distributed Arithmetic Based K-Best List Sphere Detection Algorithm for LTE Standard

K. Kalyani, S. Siva, D. Sellathambi, S. Rajaram
2013 Procedia Engineering  
From a bit error rate (BER) performance perspective, maximum likelihood (ML) detection is the preferred detection method for multiple input multiple output (MIMO) communication systems.  ...  In this paper, Distributed Arithmetic (DA) using parallel architecture based K-best List Sphere Detector (LSD) for a 3GPP LTE receiver is presented.  ...  Acknowledgment The authors would like to thank TIFAC (Technology Information Forecasting and Assessment Council) and Thiagarajar college of Engineering, Madurai for supporting this research.  ... 
doi:10.1016/j.proeng.2013.09.084 fatcat:syosifg6ingnfaem4cchhidb2y

Matrix Decomposition Architecture for MIMO Systems: Design and Implementation Trade-offs

C. Studer, P. Blosch, P. Friedli, A. Burg
2007 Asilomar Conference on Signals, Systems and Computers. Conference Record  
We present two architecture variants: one unit has processing or data compression, but can also be applied to been optimized for throughput and the other offers enhanced MIMO systems in order  ...  Matrix Decomposition Architecture for MIMO Systems: Design and Implementation Trade-offs C. Studer∗ , P. Blösch, P. Friedli, and A.  ... 
doi:10.1109/acssc.2007.4487584 fatcat:y7oc5n37dnb2hkof5dyxp36jqe

A Flexible VLSI Architecture for Extracting Diversity and Spatial Multiplexing Gains in MIMO Channels

C.-H. Yang, D. Markovic
2008 2008 IEEE International Conference on Communications  
A unified sphere decoder architecture for extracting diversity and spatial multiplexing gains in MIMO channels 2.  ...  A multi-core architecture for enhanced performance 2 Abstract-Sphere decoding algorithm is widely used in MIMO communications, because of its ability to approach maximum likelihood detection with significantly  ...  Since pipelining in the loop is considered a difficult task, this architecture can not operate at a high frequency even for a 44 system [24] .  ... 
doi:10.1109/icc.2008.142 dblp:conf/icc/YangM08 fatcat:5ej5vz6dsvh63n47zehrbfexha

Energy Efficient Group-Sort QRD Processor With On-Line Update for MIMO Channel Pre-Processing

Chenxin Zhang, Hemanth Prabhu, Yangxurui Liu, Liang Liu, Ove Edfors, Viktor Owall
2015 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
This paper presents a Sorted QR-Decomposition (SQRD) processor for 3GPP LTE-A system.  ...  It achieves energyefficiency by co-optimizing techniques, such as heterogeneous processing, reconfigurable architecture, and dual-supply voltage operation.  ...  Moreover, data-level parallelism in MIMO-OFDM systems is exploited to enable high processing throughput and energy efficiency.  ... 
doi:10.1109/tcsi.2015.2402936 fatcat:6vvfouh2g5f5rmou735uy46nfy

A VLSI 8ո MIMO Near-ML Decoder Engine

Geoff Knagge, Mark Bickerstaff, Brett Ninness, Steven R. Weller, Graeme Woodward
2006 Signal Processing Systems Design and Implementation (siPS), IEEE Workshop on  
practical for implementation in VLSI circuits.  ...  Multiple-Input Multiple-Output (MIMO) systems are of significant interest due to their ability to increase the capacity of wireless communications systems, but for these to be useful they must also be  ...  Fig. 3 . 3 Architecture of preprocessing unit for a 8x8 MIMO channel. Fig. 4 . 4 Rotation Calculator Unit for QR. Fig. 5 . 5 Flow of data through part 1 of the QR decomposition algorithm.  ... 
doi:10.1109/sips.2006.352614 dblp:conf/sips/KnaggeBNWW06 fatcat:g6dubxfrpvg5jjposffds56slq

A parallel hybrid merge-select sorting scheme for K-best LSD MIMO decoder on a dynamically reconfigurable processor

Zong Wang, Ahmet T. Erdogan, Tughrul Arslan
2010 21st Annual IEEE International Symposium on Personal, Indoor and Mobile Radio Communications  
In this paper, we propose a parallel hybrid merge-select sorting approach for the implementation of K-best list sphere detection (LSD) multi-input multi-output (MIMO) decoder based on a recently developed  ...  We discuss the targeted K-best LSD algorithm as well as the sorting scheme variations which have been tailored for our RICA architecture.  ...  Introduction With the increasing demand for high capacity, high spectral efficiency in modern wireless communication systems, MIMO technique which is based on multiple transceiver antennas has been or  ... 
doi:10.1109/pimrc.2010.5671769 dblp:conf/pimrc/WangEA10 fatcat:65kgicjigzeojghkhceyom7m6e

Area- and throughput-optimized VLSI architecture of sphere decoding

Markus Wenk, Lukas Bruderer, Andreas Burg, Christoph Studer
2010 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip  
Sphere decoding (SD) is a promising means for implementing high-performance data detection in multiple-input multiple-output (MIMO) wireless communication systems.  ...  In this paper, we focus on the register transfer level implementation of SD with minimum area-delay product for application in wideband MIMO communication systems, such as IEEE 802.11n, where multiple  ...  Bölcskei for their support during the design of the SD architecture.  ... 
doi:10.1109/vlsisoc.2010.5642593 dblp:conf/vlsi/WenkBBS10 fatcat:tw3j2mpm4rfrzn7qptynm4jzie

ASIP design for multiuser MIMO broadcast precoding

Shahriar Shahabuddin, Olli Silven, Markku Juntti
2017 2017 European Conference on Networks and Communications (EuCNC)  
A single core provides a throughput of 52.17 Mbps for MMSE precoding and takes an area of 87.53 kgates at 200 MHz on 90 nm technology.  ...  Transport triggered architecture (TTA) is used as the processor template and high level language is used to program the ASIP.  ...  High Level Architecture A part of the TTA processor for MU-MIMO precoding is illustrated in Fig. 3 . For readability, the whole processor figure is not given.  ... 
doi:10.1109/eucnc.2017.7980691 dblp:conf/eucnc/ShahabuddinSJ17 fatcat:rowgud3yprg5nc3kmveooryiki

Efficient MIMO preprocessor with sorting-relaxed QR decomposition and modified greedy LLL algorithm

Lirui Chen, Zuocheng Xing, Yongzhong Li, Shikai Qiu
2020 IEEE Access  
This paper proposes a high-efficient preprocessing algorithm for 16 × 16 MIMO detections.  ...  This decomposition adopts a relaxed sorting strategy together with a paralleled Givens Rotation (GR) array scheme, which can reduce the processing latency by 60% compared with conventional sorted QR decomposition  ...  A. SORTING RELAXED QR DECOMPOSITION In Algorithm 2, lines 4-20 demonstrate the sorting-relaxed QR decomposition algorithm for decomposing the channel matrix H as (2) .  ... 
doi:10.1109/access.2020.2980922 fatcat:h2ji2dvvhfgkdjhukqdfe4v5k4

A Programmable Accelerator For Next Generation Wireless Communications

Babak Daneshrad, Karim Mohammed
2009 Zenodo  
Publication in the conference proceedings of EUSIPCO, Glasgow, Scotland, 2009  ...  Other implementations use custom arithmetic datapaths to deliver optimized solutions for specific algorithms [9] . In this paper we present a MIMO decoder accelerator architecture.  ...  Matrix decomposition is critical to all these algorithms. Although there are alternative decompositions for some algorithms, QR decomposition is the most practical for hardware application.  ... 
doi:10.5281/zenodo.41790 fatcat:mnwvgp7k25hozprjicyfpq3oxm

VLSI Implementation of Hard- and Soft-Output Sphere Decoding for Wide-Band MIMO Systems [chapter]

Christoph Studer, Markus Wenk, Andreas Burg
2012 IFIP Advances in Information and Communication Technology  
Therefore, a universally applicable VLSI architecture for SD-based MIMO detection suitable for wide-band MIMO wireless communication systems must provide a robust solution allowing for the smooth adjustment  ...  Then, a VLSI architecture suitable for efficient data detection in wideband MIMO systems is presented and we argue that the optimization target for the parallelly-operating SD cores corresponds to minimizing  ...  Luethi for their contributions during the design and implementation of the SD architectures. Furthermore, the authors gratefully acknowledge the support  ... 
doi:10.1007/978-3-642-28566-0_6 fatcat:e7arpoqrp5h75gzregw56kwe7u

Algorithms and Architectures of Energy-Efficient Error-Resilient MIMO Detectors for Memory-Dominated Wireless Communication Systems

Muhammad S. Khairy, Chung-An Shen, Ahmed M. Eltawil, Fadi J. Kurdahi
2014 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
In a broadband MIMO-OFDM wireless communication system, embedded buffering memories occupy a large portion of the chip area and a significant amount of power consumption.  ...  In this paper we present the algorithm and VLSI architecture of a novel error-resilient K-Best MIMO detector based on the combined distribution of channel noise and induced errors due to VoS.  ...  High Level Architecture A high level architectural overview of the proposed design is depicted in Fig. 6 .  ... 
doi:10.1109/tcsi.2014.2298273 fatcat:ytj5vrs4urglhf3dgchpzhvkwi
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