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Hybrid Segment Approximate Multiplication for Image Processing Applications

Jamuna Ramasamy, Sathishkumar Nagarajan
2016 Circuits and Systems  
Existing static segment method based approximate multiplier is not suitable for certain accurate applications and dynamic segment method based approximate multiplier is not suitable for cost efficient  ...  The proposed approximate multipliers HSAM8 × 8 and EHSAM8 × 8 provide 99.85% and 99.999% accuracy respectively for various inputs.  ...  Hybrid Segment Approximate Multiplier (HSAM) The proposed hybrid approximate multiplier takes m consecutive bits (i.e., an m-bit segment) of an n-bit operand and selected two m-bit segments are applied  ... 
doi:10.4236/cs.2016.78147 fatcat:wi4663q3bzanxgm3v5xkkperva

EANN: Energy Adaptive Neural Networks

Salma Hassan, Sameh Attia, Khaled Nabil Salama, Hassan Mostafa
2020 Electronics  
The used techniques are precision scaling, approximate multiplier, computation skipping, neuron skipping, activation function approximation and truncated accumulation.  ...  It uses multiple approximation techniques in the hardware implementation of the neuron unit.  ...  Acknowledgments: This work was partially funded by ONE Lab at Zewail City of Science and Technology and at Cairo University, NTRA, ITIDA, ASRT, and NSERC.  ... 
doi:10.3390/electronics9050746 fatcat:4gi7wnkcozforlanwo6dnlgk3e

RAPID: AppRoximAte Pipelined Soft MultIpliers and Dividers for High-Throughput and Energy-Efficiency

Zahra Ebrahimi, Muhammad Zaid, Mark Wijtvliet, Akash Kumar
2022 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
In this paper, we propose RAPID, the first pipelined approximate multiplier and divider architecture, customized for FPGAs.  ...  Experimental results demonstrate the efficiency of the proposed pipelined and non-pipelined RAPID multipliers and dividers over accurate counterparts.  ...  ACKNOWLEDGEMENT This research is co-funded by the projects X-ReAp: Cross(X)-Layer Runtime Reconfigurable Approximate Architecture (Number  ... 
doi:10.1109/tcad.2022.3184928 fatcat:4q3p53bsrncgdlvczqq6yl3haq

Division algorithms and implementations

S.F. Obermann, M.J. Flynn
1997 IEEE transactions on computers  
Division algorithms can be divided into five classes: digit recurrence, functional iteration, very high radix, table look-up, and variable latency.  ...  An implementation of division by functional iteration can provide the lowest latency for typical multiplier latencies.  ...  ACKNOWLEDGMENTS The authors would like to thank Nhon Quach and Grant McFarland for their helpful discussions and comments.  ... 
doi:10.1109/12.609274 fatcat:3ffbiptz7nan7knlqet7rvpnra

Design Automation of Approximate Circuits With Runtime Reconfigurable Accuracy

Georgios Zervakis, Hussam Amrouch, Jorg Henkel
2020 IEEE Access  
Extensive experimental evaluation, using industry strength flow and circuits, demonstrates that our generated approximate circuits improve the energy by up to 41% for 2% error bound and by 17.5% on average  ...  In this paper, we propose and implement an automatic and circuit independent design framework that generates approximate circuits with dynamically reconfigurable accuracy at runtime.  ...  The NN is quantized at 8 bits to avoid floating point operations [60] . First, we use RETSINA to generate two approximate reconfigurable 8-bit multipliers.  ... 
doi:10.1109/access.2020.2981395 fatcat:vrm3wicelrfx5mjzarrio3do7i

Low Power High Performance Analysis For 64 Bit Arithmetical Logical Unit

Shikha Gupta*, Mrs Jigyasha Maru
2016 Zenodo  
approach for this in which we divide ALU is four sub block of 16-16 bit.  ...  The core of every embedded device and processor which in turn uses ALU as the workhorse.  ...  Basically here we are using four different eight bit ALU where 2 are accurate and one is Semi Accurate and one is Approximate.  ... 
doi:10.5281/zenodo.52497 fatcat:fabncgmnfzbrzkt4efb4vaq7vy

Array-Based Approximate Arithmetic Computing: A General Model and Applications to Multiplier and Squarer Design

Botang Shao, Peng Li
2015 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
By applying this model and using a commercial 90 nm CMOS standard cell library, we propose an approximate 16 16 fixed-width Booth multiplier that consumes 44.85% and 28.33% less energy and area compared  ...  Furthermore, it reduces average error, max error and mean squared error by 11.11%, 28.11%, and 25.00%, respectively, when compared with the most accurate reported approximate Booth multiplier and outperforms  ...  Two types of approximate multipliers exist: approximate AND-array multipliers, which utilize AND gates for partial product generation and approximate Booth multipliers, which use the modified Booth algorithm  ... 
doi:10.1109/tcsi.2015.2388839 fatcat:3fhnsamgkjf6xf6lqiil5unwte

SIMDive: Approximate SIMD Soft Multiplier-Divider for FPGAs with Tunable Accuracy [article]

Zahra Ebrahimi and Salim Ullah and Akash Kumar
2020 arXiv   pre-print
Moreover, the proposed SIMD multiplier-divider supersede accurate SIMD multiplier by achieving up to 26%, 45%, 36%, and 56% improvement in area, throughput, power, and energy, respectively.  ...  This paper, presents for the first time, an SIMD architecture based on novel multiplier and divider with tunable accuracy, targeted for Field-Programmable Gate Arrays (FPGAs).  ...  32-bit SIMD multiplier- divider and SoA multipliers/dividers implemented in SIMD fashion SIMD Basic Block Area (LUT) Throughput uS Power (mW) Energy (mJ) MUL Accurate Multiplier [25]  ... 
arXiv:2011.01148v1 fatcat:52aydq2xv5hxlovmg4it26qyqi

Low - Power and Error Tolerant Multi - Precision Approximate Multipliers using Voltage and Frequency Management Unit

Dr.V.Suresh Babu, Amrutha V.
2019 IJIREEICE  
The proposed method uses a novel approximate compressors and an algorithm to exploit them for the design of efficient approximate multipliers.  ...  inputs using generate and propagate signals.  ...  From the fundamental 4 bit approximate multiplier 8, 16 and 32 bit multiplier are computed. The 5 th and 6 th type results in low error and is used in image processing applications.  ... 
doi:10.17148/ijireeice.2019.7409 fatcat:igfkaahconeghh43nskhvvbjgm

A Reconfigurable Approximate Floating-Point Multiplier with kNN

Mi Lu
2021 figshare.com  
Previous approximate multipliers are designed using simple adders based on ML classifiers but by using a simple adder-based approximate multiplier, the level of approximation cannot change at runtime.  ...  than 3%, a rounding enhanced simple adders-based approximate multiplier can save area by 65.9% and a reconfigurable adderbased approximate multiplier with rounding can reduce the average delay and energy  ...  The 32-bits can be divided into three parts: 1-bit for the sign, 8-bits for the exponent and 23-bits for the mantissa.  ... 
doi:10.6084/m9.figshare.14143841.v1 fatcat:3bs2d67v75ak7jbhaqth627vqq

Optimal Architecture of Floating-Point Arithmetic for Neural Network Training Processors

Muhammad Junaid, Saad Arslan, TaeGeon Lee, HyungWon Kim
2022 Sensors  
The proposed architecture incorporates training in 32 bits, 24 bits, 16 bits, and mixed precisions to find the optimal floating-point format for low power and smaller-sized edge device.  ...  Compared with 32-bit architecture, the size and the energy are reduced by 4.7 and 3.91 times, respectively.  ...  5.019 Table 7 . 7 Comparison of accuracy and dynamic power using the algorithm.  ... 
doi:10.3390/s22031230 pmid:35161975 pmcid:PMC8840430 fatcat:e5yh4ccwijf6ddhbhusyfq4xtq

Power/Area Analysis of a FPGA-Based Open-Source Processor using Partial Dynamic Reconfiguration

Izhar Zaidi, Atukem Nabina, C.N. Canagarajah, Jose Nunez-Yanez
2008 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools  
The latency of this multiplier is one clock cycle [9] . The selected divider module performs signed/unsigned 64-bit by 32-bit division taking 36 clock cycles and leaving no remainder.  ...  The multiplier module selected for this work implements 32x32 bit multiplication. It takes two signed or unsigned numbers as input and produces a 64-bit result.  ... 
doi:10.1109/dsd.2008.92 dblp:conf/dsd/ZaidiNCN08 fatcat:dz4gpu5arnfi7lod456dpwqaae

DRUM: A Dynamic Range Unbiased Multiplier for approximate applications

Soheil Hashemi, R. Iris Bahar, Sherief Reda
2015 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)  
Since multiplication is an essential arithmetic operation for these applications, in this paper we focus specifically on this operation and propose a novel approximate multiplier with a dynamic range selection  ...  Our approximate multiplier design is also scalable, enabling designers to parameterize it depending on their accuracy and power targets.  ...  In our design, we propose a dynamic and fast bit selection scheme to reduce the size of the multiplier while introducing a bounded unbiased error to the multiplication result.  ... 
doi:10.1109/iccad.2015.7372600 dblp:conf/iccad/HashemiBR15 fatcat:s5tqxzpvl5e7hlq6wxi5id34zm

Comparative Analysis of Polynomial and Rational Approximations of Hyperbolic Tangent Function for VLSI Implementation [article]

Mahesh Chandra
2020 arXiv   pre-print
This paper presents comparative analysis of polynomial and rational methods and their hardware implementation.  ...  Even though, various methods and implementations of tanh activation function have been published, a comparative study is missing.  ...  multipliers (one for each bit).  ... 
arXiv:2007.11976v2 fatcat:wwrylsudjvgvfepkgitimqoa7i

An Architecture of Area-Effective High Radix Floating-Point Divider with Low Power Consumption

Yuheng Yang, Qing Yuan, Jian Liu
2021 IEEE Access  
The dynamic power consumption of the divider is only 0.848mW at 250MHz.  ...  The latency and area cost of the divider are linear with the radix number, which solves the problem that the quotient digits selection tables in high-radix divider have high area cost.  ...  registers, which are used to store the dividend, divisor and quotient digits. rs is the temporary register with 25-bit, which are used to store the 24-bit value and 1-bit sign of the partial remainder  ... 
doi:10.1109/access.2021.3065063 fatcat:pz3sqfl3kzh4dhy25jcmxkqoqq
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