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Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOI

Sunghyun Park, Tushar Krishna, Chia-Hsin Chen, Bhavya Daya, Anantha Chandrakasan, Li-Shiuan Peh
2012 Proceedings of the 49th Annual Design Automation Conference on - DAC '12  
In this paper, we present a case study of our chip prototype of a 16-node 4x4 mesh NoC fabricated in 45nm SOI CMOS that aims to simultaneously optimize energy-latency-throughput for unicasts, multicasts  ...  We first define and analyze the theoretical limits of a mesh NoC in latency, throughput and energy, then describe how we approach these limits through a combination of microarchitecture and circuit techniques  ...  PROPOSED NOC CHIP DESIGN This section describes the design of our chip prototype. Figure 2 shows our fabricated 16-node 4x4 NoC.  ... 
doi:10.1145/2228360.2228431 dblp:conf/dac/ParkKCDCP12 fatcat:appbb3sepfbbjm3ftwjfouqdyq

SCORPIO: A 36-core research chip demonstrating snoopy coherence on a scalable mesh NoC with in-network ordering

Bhavya K. Daya, Chia-Hsin Owen Chen, Suvinay Subramanian, Woo-Cheol Kwon, Sunghyun Park, Tushar Krishna, Jim Holt, Anantha P. Chandrakasan, Li-Shiuan Peh
2014 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)  
The SCORPIO architecture is incorporated in an 11 mm-by-13 mm chip prototype, fabricated in IBM 45nm SOI technology, comprising 36 Freescale e200 Power Architecture TM cores with private L1 and L2 caches  ...  The chip prototype achieves a post synthesis operating frequency of 1 GHz (833 MHz post-layout) with an estimated power of 28.8 W (768 mW per tile), while the network consumes only 10% of tile area and  ...  Acknowledgements SCORPIO is a large project involving 6 students collaborating closely.  ... 
doi:10.1109/isca.2014.6853232 dblp:conf/isca/DayaCSKPKHCP14 fatcat:m62dljrpebdjjefmp2bos4abya

SCORPIO

Bhavya K. Daya, Chia-Hsin Owen Chen, Suvinay Subramanian, Woo-Cheol Kwon, Sunghyun Park, Tushar Krishna, Jim Holt, Anantha P. Chandrakasan, Li-Shiuan Peh
2014 SIGARCH Computer Architecture News  
The SCORPIO architecture is incorporated in an 11 mm-by-13 mm chip prototype, fabricated in IBM 45nm SOI technology, comprising 36 Freescale e200 Power Architecture TM cores with private L1 and L2 caches  ...  The chip prototype achieves a post synthesis operating frequency of 1 GHz (833 MHz post-layout) with an estimated power of 28.8 W (768 mW per tile), while the network consumes only 10% of tile area and  ...  Acknowledgements SCORPIO is a large project involving 6 students collaborating closely.  ... 
doi:10.1145/2678373.2665680 fatcat:62h627vqlzam7defi3pakoyv6y

Nano-Photonic Networks-on-Chip for Future Chip Multiprocessors [chapter]

Cheng Li, Paul V. Gratz, Samuel Palermo
2015 More than Moore Technologies for Next Generation Computer Design  
Crossbar or Clos architectures, in which the interconnect is fully photonic [15, 16, 17, 18, 19, 20, 21, 22, 23] .  ...  of sub-sets of cores in photonic subnets.  ...  Many photonic NoCs globally route waveguides in a bundle, connecting all the tiles in the CMP [16, 19, 20, 21] .  ... 
doi:10.1007/978-1-4939-2163-8_7 fatcat:a46olb47unbxrgov5rcknn7sly

Memory leads the way to better computing

H.-S. Philip Wong, Sayeef Salahuddin
2015 Nature Nanotechnology  
The report itself was drawn from the results of a series of meetings over the second half of 2007, and as such reflects a snapshot in time.  ...  Further, the report itself was assembled in just a few months at the beginning of 2008 from input by the participants.  ...  The optical Network on-chip (NoC) network topology can be assumed to be a mesh, or some derivative thereof, such as a torus.  ... 
doi:10.1038/nnano.2015.29 pmid:25740127 fatcat:d6iiuuwcozbxlgn4kxxzdzwd4m

Sturcken_columbia_0054D_11175.pdf [article]

2017
Custom integrated circuits are designed and fabricated in 45nm-SOI to provide the control system and power-train necessary to drive the power inductors.  ...  A silicon interposer is designed and fabricated in collaboration with IBM Research to integrate custom power inductors by 2.5D chip stacking, enabling power conversion with current density greater than  ...  chip in a 45nm SOI process to experimentally verifyproper converter operation.  ... 
doi:10.7916/d8sx6mhx fatcat:vvsskyawl5c3nimbou4shgyx4y

Design and performance optimization of asynchronous networks-on-chip

Weiwei Jiang
2018
As a result, there has been significant recent interest in combing the notion of asynchrony with NoC designs.  ...  The number of transistors on individual chips is already in the multi-billion range, and a greatly increasing number of components are being integrated onto a single chip.  ...  At the level of network routing, adaptive routing allows data to be routed around the router with failure [181] ; The first prototype chip integrates 4 clusters, each with 16 synchronous processors,  ... 
doi:10.7916/d8rf7b21 fatcat:tvsdrghsyffcpcb6u7xzx54nyq

INGEGNERIA ELETTRONICA, TELECOMUNICAZIONI E TECNOLOGIE DELL'INFORMAZIONE Ciclo XXVIII Memory Hierarchy Design for Next Generation Scalable Many-core Platforms Coordinatore Dottorato Relatore Memory Hierarchy Design for Next Generation Scalable Many-core Platforms

Vanelli Alessandro, Coralli, Luca Benini, Erfan Azarkhish
2016 unpublished
With the emergence of heterogeneous Three Dimensional (3D) Integration based on through-silicon-vias (TSV), this situation has started to recover in the past years.  ...  In addition, by moving a part of the computation to where data resides, in the 3D-stacked memory context, we demonstrate further energy and performance improvement opportunities.  ...  PE die (PD) consists of 16 STxP70 processing elements [44] connected to a mesh NoC with 16 switches. 3D-NUMA is attached to this NoC through its NIs.For thermal analysis, ambient temperature is assumed  ... 
fatcat:e2rk56rc4naoljdxduijinhqgy

HETEROGENEOUS ARCHITECTURES FOR PARALLEL ACCELERATION Heterogeneous Architectures for Parallel Acceleration

Presentata, Dott Conti, Coordinatore Dottorato, Relatore Prof, Vanelli Alessandro, Coralli, Luca Benini, Francesco Conti, W Shakespeare, Hamlet
unpublished
This platform, which is silicon-proven, can lead to more than 100× improvement in terms of energy efficiency with respect to typical computing nodes used within the same domain, enabling the application  ...  methodologies to introduce it with little or no loss in terms of flexibility.  ...  NoC nodes.  ... 
fatcat:azdg7uimg5e6pjieq6q4gg7z2y

Performance Variation in Digital Systems:Workload Dependent Modeling and Mitigation [article]

(:Unkn) Unknown, National Technological University Of Athens
2021
of the various on-chip modules (as well as the gateway to the off-chip components), a fault in the NoC can render the entire chip useless 6 .  ...  We focus on the SRAM memory of a Network on Chip (NoC) router since NoCs are in general crucial components for the operation of a multicore processor; given that the NoC constitutes the communication backbone  ...  A depicture of the above, drawn for relevant work [185] , is shown in Figure A. 1. Failure Rate is defined as the number of failures on a system during a specific time interval.  ... 
doi:10.26240/heal.ntua.21941 fatcat:6i5vt2rk3jaabdxtublpupx43y

Contribution à la conception de systèmes numériques adaptatifs

Pascal Benoit, Pascal
unpublished
IMPLEMENTATION OF THE GAME-THEORETIC CONTROLLER In the following, we analyze the efficiency and the complexity of the game theoretic approach in a concrete context.  ...  Interconnection The PEs previously described are interconnected by a Network-on-Chip (NoC) [9, 10, 11, 12] . A NoC is composed of Network Interfaces (NI), routing nodes and links.  ...  The efficiency of the approach relies on the parallelism of the executed code that is, in practice, fairly limited.  ... 
fatcat:mqymictyzzadvj5g42xo7kbbda