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Applying architectural vulnerability Analysis to hard faults in the microprocessor

Fred A. Bower, Derek Hower, Mahmut Yilmaz, Daniel J. Sorin, Sule Ozev
2006 Performance Evaluation Review  
In this paper, we present a new metric, Hard-Fault Architectural Vulnerability Factor (H-AVF), to allow designers to more effectively compare alternate hard-fault tolerance schemes.  ...  In order to provide intuition on the use of H-AVF as a metric, we evaluate fault-tolerant level-1 data cache and register file implementations using error correcting codes and a faulttolerant adder using  ...  ACKNOWLEDGMENTS This work is supported in part by the National Science Foundation under grants CCF-0444516 and CCR-0309164, the National Aeronautics and Space Administration under grant NNG04GQ06G, Intel  ... 
doi:10.1145/1140103.1140327 fatcat:jx4fv3g3s5gope2zcjmbzqynpm

Applying architectural vulnerability Analysis to hard faults in the microprocessor

Fred A. Bower, Derek Hower, Mahmut Yilmaz, Daniel J. Sorin, Sule Ozev
2006 Proceedings of the joint international conference on Measurement and modeling of computer systems - SIGMETRICS '06/Performance '06  
In this paper, we present a new metric, Hard-Fault Architectural Vulnerability Factor (H-AVF), to allow designers to more effectively compare alternate hard-fault tolerance schemes.  ...  In order to provide intuition on the use of H-AVF as a metric, we evaluate fault-tolerant level-1 data cache and register file implementations using error correcting codes and a faulttolerant adder using  ...  ACKNOWLEDGMENTS This work is supported in part by the National Science Foundation under grants CCF-0444516 and CCR-0309164, the National Aeronautics and Space Administration under grant NNG04GQ06G, Intel  ... 
doi:10.1145/1140277.1140327 dblp:conf/sigmetrics/BowerHYSO06 fatcat:d3nih2l4bbci5fpmtcftycvx44

Global Signal Vulnerability (GSV) Analysis for Selective State Element Hardening in Modern Microprocessors

Michail Maniatakos, Chandrasekharan Tirumurti, Rajesh Galivanche, Yiorgos Makris
2012 IEEE transactions on computers  
Global Signal Vulnerability (GSV) analysis is a novel method for assessing the susceptibility of modern microprocessor state elements to failures in the field of operation.  ...  GSV analysis operates either at the Register Transfer (RT-) or at the Gate-Level, offering increased accuracy in contrast to methods which compute the architectural vulnerability of registers through highlevel  ...  RANKING BASED ON ARCHITECTURAL VULNERABILITY FACTOR (AVF) The notion of Architectural Vulnerability Factor has been extensively used in the past to rank state elements based on their criticality to program  ... 
doi:10.1109/tc.2011.172 fatcat:6n2my6zva5fhjfofadxl7v4upq

Compiler-Directed Soft Error Mitigation for Embedded Systems

A. Martinez-Alvarez, S. Cuenca-Asensi, F. Restrepo-Calle, F. R. P. Pinto, H. Guzman-Miranda, M. A. Aguirre
2012 IEEE Transactions on Dependable and Secure Computing  
It is based on a generic microprocessor architecture that facilitates the implementation of software-based techniques, providing a uniform isolated-from-target hardening core that allows the automatic  ...  The protection of processor-based systems to mitigate the harmful effect of transient faults (soft errors) is gaining importance as technology shrinks.  ...  This feature permits to apply the fault-tolerance techniques using a microprocessor agnostic methodology.  ... 
doi:10.1109/tdsc.2011.54 fatcat:72lpyhcoi5eozhneoj3cth74wa

SyRA: Early System Reliability Analysis for Cross-Layer Soft Errors Resilience in Memory Arrays of Microprocessor Systems

A. Vallero, A. Savino, A. Chatzidimitriou, M. Kaliorakis, M. Kooli, M. Riera, M. Anglada, G. Di Natale, A. Bosio, R. Canal, A. Gonzalez, D. Gizopoulos (+2 others)
2019 IEEE transactions on computers  
The simulation time is significantly lower than micro-architecture level or RTL fault-injection experiments with an accuracy high enough to take effective design decisions.  ...  To demonstrate the capability of SyRA, we analyzed the reliability of a set of microprocessor-based systems characterized by different microprocessor architectures (i.e., Intel x86, ARM Cortex-A15, ARM  ...  They model how hardware vulnerable faults identified in the HAL can be modeled in the software architecture layer (SAL).  ... 
doi:10.1109/tc.2018.2887225 fatcat:dwukqo5iwnejjge6nhy3ihaaha

Cross-layer early reliability evaluation: Challenges and promises

S. Di Carlo, A. Vallero, D. Gizopoulos, G. Di Natale, A. Gonzalez, R. Canal, R. Mariani, M. Pipponzi, Arnaud Grasset, Philippe Bonnot, Frank Reichenbach, G. Rafiq (+1 others)
2014 2014 IEEE 20th International On-Line Testing Symposium (IOLTS)  
It has been also supported in part by EU's European Social Fund (ESF) and Greek national funds under the "Thales/HOLISTIC" project.  ...  ACKNOWLEDGMENT This paper has been fully supported by the 7th Framework Program of the European Union through the CLERECO Project, under Grant Agreement 611404.  ...  [16] , apply statistical analysis using a detailed simulator to analyze the AVF behavior at large scale.  ... 
doi:10.1109/iolts.2014.6873704 dblp:conf/iolts/CarloVGNGCMPGBRRL14 fatcat:islnaxasjrcg5prwegbcqtbxaa

A Systematic Review of Fault Injection Attacks on IoT Systems

Aakash Gangolli, Qusay H. Mahmoud, Akramul Azim
2022 Electronics  
The methods proposed in the literature to handle fault injection attacks on IoT systems vary from hardware-based attack detection using system-level properties to analyzing the IoT software for vulnerabilities  ...  This paper provides a systematic review of the various techniques proposed in the literature to counter fault injection attacks at both the system level and the software level to identify their limitations  ...  Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/electronics11132023 fatcat:ic5ytu5nlnfpnhlualafdbcztu

Online diagnosis of hard faults in microprocessors

Fred A. Bower, Daniel J. Sorin, Sule Ozev
2007 ACM Transactions on Architecture and Code Optimization (TACO)  
A hard fault in an FDU quickly leads to an above-threshold error counter for that FDU and thus diagnoses the fault.  ...  To do this, we must: detect and correct errors, diagnose hard faults at the field deconfigurable unit (FDU) granularity, and deconfigure FDUs with hard faults.  ...  ACKNOWLEDGMENTS We thank Alvy Lebeck and the rest of the Duke Architecture Reading Group for helpful feedback on this paper.  ... 
doi:10.1145/1250727.1250728 fatcat:lq2g3lffebaatixrm7rmycqdbe

Autonomic Microprocessor Execution via Self-Repairing Arrays

F.A. Bower, S. Ozev, D.J. Sorin
2005 IEEE Transactions on Dependable and Secure Computing  
To achieve high reliability despite hard faults that occur during operation and to achieve high yield despite defects introduced at fabrication, a microprocessor must be able to tolerate hard faults.  ...  When hard faults are present in arrays, due to operational faults or fabrication defects, SRAS schemes outperform BER due to not having to frequently flush the pipeline.  ...  This paper partially includes research that appeared in the Proceedings of the 2004 International Conference on Dependable Systems and Networks [8] .  ... 
doi:10.1109/tdsc.2005.44 fatcat:qmfdkcjvhbejzdehbxaqro4c4m

Selective SWIFT-R

Felipe Restrepo-Calle, Antonio Martínez-Álvarez, Sergio Cuenca-Asensi, Antonio Jimeno-Morenilla
2013 Journal of electronic testing  
However, they have also made microprocessors more susceptible to transient faults induced by radiation.  ...  Commercial off-the-shelf microprocessors are the core of low-cost embedded systems due to their programmability and cost-effectiveness.  ...  Our proposal allows applying the protection to different register subsets from the microprocessor register file looking for a reduction in the overheads but keeping a high fault coverage.  ... 
doi:10.1007/s10836-013-5416-6 fatcat:gzdgn2qvczehraj6vargyjki54

Bayesian network early reliability evaluation analysis for both permanent and transient faults

A. Vallero, A. Savino, S. Tselonis, N. Foutris, M. Kaliorakis, G. Politano, D. Gizopoulos, S. Di Carlo
2015 2015 IEEE 21st International On-Line Testing Symposium (IOLTS)  
As a consequence it can be a valid alternative to fault injection, especially in the early stage of the design.  ...  Current approaches mainly rely on time consuming fault injections experiments that prevent their usage in the early stage of the design process, when fast estimations are required in order to take design  ...  For a preliminary analysis, hardware faults have been just injected into microprocessor physical registers belonging to the Integer Register File.  ... 
doi:10.1109/iolts.2015.7229819 dblp:conf/iolts/ValleroSTFKPGC15 fatcat:35zhik76dvecvnycogiv7vwif4

A Low-Cost, Radiation-Hardened Method for Pipeline Protection in Microprocessors

Yang Lin, Mark Zwolinski, Basel Halak
2016 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
A gate-level transient fault injection and analysis technique is used to evaluate the error-tolerance capability of the proposed hardened pipeline design.  ...  The proposed pipeline protection technique is implemented in an OpenRISC microprocessor in 65nm technology.  ...  The authors are with Electronics and Computer Science, Faculty of Physical Science and Engineering, University of Southampton, Southampton, UK, SO17 1BJ. E-mail: {yl5g09,mz, bh9}@ecs.soton.ac.uk  ... 
doi:10.1109/tvlsi.2015.2475167 fatcat:rtp7k2y43vazpo445hr4rb25ve

A compiler-based infrastructure for fault-tolerant co-design

Felipe Restrepo-Calle, Antonio Martínez-Álvarez, Hipólito Guzmán-Miranda, F. R. Palomo, M. A. Aguirre, Sergio Cuenca-Asensi
2010 Proceedings of the 13th International Workshop on Software & Compilers for Embedded Systems - SCOPES '10  
In this way, these methods can be implemented in an architecture independent way and can easily integrate new protection mechanisms to automatically produce hardened code.  ...  The tool-chain is complemented by a hardware fault emulation tool that allows to measure the fault coverage of the different solutions running on the real system.  ...  based analysis and code-injection routines. • automatic reallocation/minimization of architecture resources to optimize fault coverage.  ... 
doi:10.1145/1811212.1811218 dblp:conf/scopes/Restrepo-CalleMGPAC10 fatcat:tfvgeokbnnbj3maoflxu3hiauu

Application-driven co-design of fault-tolerant industrial systems

F. Restrepo-Calle, A. Martinez-Alvarez, H. Guzman-Miranday, F. R. Palomoy, S. Cuenca-As
2010 2010 IEEE International Symposium on Industrial Electronics  
As a case study, we selected a soft-micro (PicoBlaze) widely used in FPGA-based industrial systems, and a fault tolerant version of the matrix multiplication algorithm was developed.  ...  Using the proposed methodology, the design was guided by the requirements of the application, leading us to explore several trade-offs among reliability, performance and cost.  ...  The work presented here has been carried out thanks to the support of the research projects 'Aceleración de algoritmos industriales y de seguridad en entornos críticos mediante hardware: Aplicación al  ... 
doi:10.1109/isie.2010.5637483 fatcat:z4eavmlkonavvi5fbjggzi3odu

Understanding soft error propagation using Efficient vulnerability-driven fault injection

Xin Xu, Man-Lap Li
2012 IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2012)  
To evaluate, statistical fault injection (SFI) is often used to estimate the error coverage of the underlying method.  ...  This paper makes the observation that many derated errors can be gracefully avoided to allow the fault injection campaign to focus on likely non-derated faults that stress the method-under-test.  ...  Critical Fault is made up of two phases: vulnerability analysis and guided fault injection. Vulnerability analysis (VA) is similar to the architecturally correct execution (ACE) analysis.  ... 
doi:10.1109/dsn.2012.6263923 dblp:conf/dsn/XuL12 fatcat:e7k7kwagszalxdalohl25ow6pu
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