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Applying WCET Analysis at Architectural Level

Olivier Gilles, Jérôme Hugues, Marc Herbstritt
2008
We list the different steps to successfully apply WCET analysis directly from model, to limit user intervention.  ...  WCET analysis is usually a complex and time-consuming activity. It becomes increasingly complex when one also considers code generation strategies from high-level models.  ...  In particular, subprogram WCET or code size cannot be guessed reliably at design level.  ... 
doi:10.4230/oasics.wcet.2008.1665 fatcat:53hvpliwcjez5h5gzj6565pwxi

Testing Implementation Soundness of a WCET Analysis Tool [chapter]

Reinhard Wilhelm, Markus Pister, Gernot Gebhard, Daniel Kästner
2020 A Journey of Embedded and Cyber-Physical Systems  
In the case of a static WCET analysis tool, the testing effort is applied at tool-qualification time when ample time is available.  ...  Such architectures show a more regular hardware design. WCET Analysis Performance-enhancing architectural components such as caches, pipelines, and speculation have made WCET analysis difficult.  ... 
doi:10.1007/978-3-030-47487-4_2 fatcat:qvnt6ltauzcjjpmtgro7r3tpa4

Migration-aware WCET estimation for heterogeneous multi-cores

Peter Munk, Jan Richling
2014 ACM SIGBED Review  
We differentiate between two levels of heterogeneity, namely same instruction set architecture (ISA) with different performance characteristics and different ISAs.  ...  Our approach is to split the WCET of a task into parts and derive the WCET for all parts on all individual core architectures.  ...  the overall WCET of a task into multiple parts. • We discuss implementation concepts of our partitioning idea at three levels, namely on (a) WCET analysis level, (b) compiler level, and (c) library level  ... 
doi:10.1145/2692385.2692388 fatcat:qosyzig5jrcxvi5iiqcq76v34u

Integrated Worst-Case Execution Time Estimation of Multicore Applications

Dumitru Potop-Butucaru, Isabelle Puaut, Marc Herbstritt
2013 Worst-Case Execution Time Analysis  
Worst-case execution time (WCET) analysis has reached a high level of precision in the analysis of sequential programs executing on single-cores.  ...  In this paper we extend a state-of-the-art WCET analysis technique to compute tight WCETs estimates of parallel applications running on multicores.  ...  During the hardware-level analysis phase, our WCET analysis method applies instruction cache, data cache, and pipeline analysis on the two CFGs core1_body and core2_body.  ... 
doi:10.4230/oasics.wcet.2013.21 dblp:conf/wcet/Potop-ButucaruP13 fatcat:qkir7t55mfgexczbptxlpcn3fy

The Heptane Static Worst-Case Execution Time Estimation Tool

Damien Hardy, Benjamin Rouxel, Isabelle Puaut, Marc Herbstritt
2017 Worst-Case Execution Time Analysis  
Heptane is an open-source software program that estimates upper bounds of execution times on MIPS and ARM v7 architectures, offered to the WCET estimation community to experiment new WCET estimation techniques  ...  The software architecture of Heptane was designed to be as modular and extensible as possible to facilitate the integration of new approaches.  ...  HeptaneAnalysis applies low-level and high-level analyses to produce the WCET estimate.  ... 
doi:10.4230/oasics.wcet.2017.8 dblp:conf/wcet/HardyRP17 fatcat:uw2eajb3frh4db5knsdclpomge

Calculation of worst-case execution time for multicore processors using deterministic execution

Hamid Mushtaq, Zaid Al-Ars, Koen Bertels
2015 2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)  
Worst-case execution time (WCET) analysis has reached a high level of precision in the analysis of sequential programs executing on single-cores.  ...  In this paper we extend a state-of-the-art WCET analysis technique to compute tight WCETs estimates of parallel applications running on multicores.  ...  During the hardware-level analysis phase, our WCET analysis method applies instruction cache, data cache, and pipeline analysis on the two CFGs core1_body and core2_body.  ... 
doi:10.1109/patmos.2015.7347584 dblp:conf/patmos/MushtaqAB15 fatcat:fl7tbwaeezbcngayfxmhj5m6ge

Hardware support for WCET analysis of hard real-time multicore systems

Marco Paolieri, Eduardo Quiñones, Francisco J. Cazorla, Guillem Bernat, Mateo Valero
2009 SIGARCH Computer Architecture News  
In this paper we propose a multicore architecture with shared resources that allows the execution of applications with hard real-time and non hard real-time constraints at the same time, providing time  ...  Moreover our architecture proposal provides high-performance for the non hard real-time tasks.  ...  Moreover, our proposal can use current WCET analysis tools without requiring any modification, so whatever analysis tool is used in single-core systems can be applied to our multicore architecture.  ... 
doi:10.1145/1555815.1555764 fatcat:m7rjwil5angjnhaltopzlnlszi

Applying static timing analysis to component architectures

Pascal Montag, Steffen Görzig, Paul Levi
2006 Proceedings of the 2006 international workshop on Software engineering for automotive systems - SEAS '06  
The feasibility of the introduced concept is shown in the prototype architecture and a prototype application.  ...  The increase in software functions and software complexity of automotive applications requires appropriate software architectures.  ...  The focus of this paper is the calculation of the WCET on the single task level. The ECU level calculation which is performed by a schedulability analysis is based on this WCET estimation.  ... 
doi:10.1145/1138474.1138480 fatcat:ecaxdpme3jhsziyclyt4vyxvam

Hardware support for WCET analysis of hard real-time multicore systems

Marco Paolieri, Eduardo Quiñones, Francisco J. Cazorla, Guillem Bernat, Mateo Valero
2009 Proceedings of the 36th annual international symposium on Computer architecture - ISCA '09  
In this paper we propose a multicore architecture with shared resources that allows the execution of applications with hard real-time and non hard real-time constraints at the same time, providing time  ...  Moreover our architecture proposal provides high-performance for the non hard real-time tasks.  ...  Moreover, our proposal can use current WCET analysis tools without requiring any modification, so whatever analysis tool is used in single-core systems can be applied to our multicore architecture.  ... 
doi:10.1145/1555754.1555764 dblp:conf/isca/PaolieriQCBV09 fatcat:jm6din3libcjvkhqoiiwtnd5mq

Tracing Flow Information for Tighter WCET Estimation: Application to Vectorization

Hanbing Li, Isabelle Puaut, Erven Rohou
2015 2015 IEEE 21st International Conference on Embedded and Real-Time Computing Systems and Applications  
Standard static WCET estimation techniques establish a WCET bound from an analysis of the machine code, taking into account additional flow information provided at source code level, either by the programmer  ...  or from static code analysis.  ...  Then it is used to build a WCET analysis tool by Barany et al. [19] . This tool can transform the flow information in the source code level to the WCET analysis on different levels.  ... 
doi:10.1109/rtcsa.2015.18 dblp:conf/rtcsa/LiPR15 fatcat:py5wc54y4zg7ro26odypbrwwce

Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach

Martin Schoeberl, Pascal Schleuniger, Wolfgang Puffitsch, Florian Brandner, Christian W. Probst, Marc Herbstritt
2011 Design, Automation, and Test in Europe  
Many architectural features that increase the average case performance are hard to be modeled for the WCET analysis.  ...  The instruction cache is organized as a method cache and the data cache is organized as a split cache in order to simplify the cache WCET analysis.  ...  The modeling of memory hierarchies with multiple levels of caches is critical for practical WCET analysis.  ... 
doi:10.4230/oasics.ppes.2011.11 dblp:conf/date/SchoeberlSPBP11 fatcat:f3mbwaezuvbeppzfkclo426g2q

Time-predictable chip-multiprocessor design

Martin Schoeberl
2010 2010 Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers  
The static TDMA schedule can be integrated into the WCET analysis.  ...  Real-time systems need time-predictable platforms to enable static worst-case execution time (WCET) analysis.  ...  The main advantage of directly executing bytecode instructions is that WCET analysis can be performed at the bytecode level. The WCET tool WCA [23] is part of the JOP distribution.  ... 
doi:10.1109/acssc.2010.5757923 fatcat:4fklqnckwbekxltbqn63hpn5n4

parMERASA -- Multi-core Execution of Parallelised Hard Real-Time Applications Supporting Analysability

T. Ungerer, C. Bradatsch, M. Gerdes, F. Kluge, R. Jahr, J. Mische, J. Fernandes, P.G. Zaykov, Z. Petrov, B. Boddeker, S. Kehr, H. Regler (+16 others)
2013 2013 Euromicro Conference on Digital System Design  
We aim to achieve a breakthrough in techniques for parallelization of industrial hard real-time programs, provide hard real-time support in system software, WCET analysis and verification tools for multi-cores  ...  System Architecture One of the main responsibilities of the parMERASA system architecture is to ensure that the timing assumptions done at the application level are maintained.  ...  This metric will be demonstrated by applying the parMERASA WCET analysis tools on the avionic, automotive, and construction machinery case studies.  ... 
doi:10.1109/dsd.2013.46 dblp:conf/dsd/UngererBGKJMFZPBKRHROCBSBLGQPACURP13 fatcat:sc4uy2gpavcgtgj4gz3wxe3oym

A Survey of Worst-Case Execution Time Analysis for Real-Time Java

Trevor Harmon, Raymond Klefstad
2007 2007 IEEE International Parallel and Distributed Processing Symposium  
One technique involves a static analysis to place an upper bound on worst-case execution time (WCET). Other techniques aim for new architectures and algorithms that reduce the WCET.  ...  At the same time, there is a growing interest in using Java for real-time systems. Several WCET analysis prototypes for Java have been created, and more are under development.  ...  Other Work in WCET Analysis for Java Portability, low-level analysis, and high-level analysis are where most WCET research for Java has been applied.  ... 
doi:10.1109/ipdps.2007.370422 dblp:conf/ipps/HarmonK07a fatcat:sxkwhzz5eja4hggj2fifvywahe

Is time predictability quantifiable?

Martin Schoeberl
2012 2012 International Conference on Embedded Computer Systems (SAMOS)  
We can only compare the worst-case execution time bounds of different architectures.  ...  Computer architects and researchers in the realtime domain start to investigate processors and architectures optimized for real-time systems.  ...  The authors extract ILP at the microcode level and schedule the instructions statically -similar to a VLIW architecture.  ... 
doi:10.1109/samos.2012.6404196 dblp:conf/samos/Schoeberl12 fatcat:44rhizvp3fdtbi4ajif5xv6bz4
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