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A light-weight Network-on-Chip architecture for dynamically reconfigurable systems

Simone Corbetta, Vincenzo Rana, Marco Domenico Santambrogio, Donatella Sciuto
2008 2008 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation  
On-chip communication design is a complex task, since the communication requirements and the complexity of the target application are high.  ...  The proposed approach is a tile-based Network-on-Chip in which the communication layer is completely decoupled from the computational one.  ...  The Network-on-Chip approach has been proposed in [9] as a novel design paradigm for Systemon-Chip applications.  ... 
doi:10.1109/icsamos.2008.4664846 dblp:conf/samos/CorbettaRSS08 fatcat:3b7s5qhipveedkdw5w7osudhje

Run-time energy management of manycore systems through reconfigurable interconnects

Jie Meng, Chao Chen, Ayse Kivilcim Coskun, Ajay Joshi
2011 Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI - GLSVLSI '11  
The active on-chip network channel width has a direct impact on the cache and memory access latency in manycore processors.  ...  This paper proposes a novel, low-cost method to reconfigure the network channel width at run time to maximize energy efficiency of applications.  ...  The network-on-chip (NoC) infrastructure has a direct impact on application performance and energy efficiency in manycore systems.  ... 
doi:10.1145/1973009.1973019 dblp:conf/glvlsi/MengCCJ11 fatcat:y2nlu5v7lzdjfglf26zxk5gde4

Transport Layer Assisted Routing for Non-Stationary Irregular mesh of thermal-aware 3D Network-on-Chip systems

Chih-Hao Chao, Tsu-Chu Yin, Shu-Yen Lin, An-Yeu Wu
2011 2011 IEEE International SOC Conference  
Thermal issue is important for 3D Network-on-Chip systems. To ensure thermal safety, run-time thermal management is required.  ...  However, the regulation of temperature requires throttling of the near-overheated router, which makes the topology become Non-Stationary Irregular mesh (NSI-mesh).  ...  Network-on-Chip (NoC) has been proposed as a novel and practical infrastructure.  ... 
doi:10.1109/socc.2011.6085086 dblp:conf/socc/ChaoYLW11 fatcat:pxzcrce3hba2bbcsoyrwrxpxc4

A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication [chapter]

Vincenzo Rana, David Atienza, Marco Domenico Santambrogio, Donatella Sciuto, Giovanni De Micheli
2010 IFIP Advances in Information and Communication Technology  
Network-on-Chip (NoC) has emerged as a very promising paradigm for designing scalable communication architecture for Systemson-Chips (SoCs).  ...  However, NoCs designed to fulfill the bandwidth requirements between the cores of an SoC for a certain set of running applications may be highly sub-optimal for another set of applications.  ...  Acknowledgments This work was partially supported by the HiPEAC network of excellence (, the Swiss NSF Research Grant 20021-109450/1 and Spanish Government Research Grants TIN2005-5619,  ... 
doi:10.1007/978-3-642-12267-5_13 fatcat:l44c3qxzz5aahifl62z2iosszi

Power-aware mapping for reconfigurable NoC architectures

Mehdi Modarressi, Hamid Sarbazi-Azad
2007 2007 25th International Conference on Computer Design  
A core mapping method for reconfigurable network-on-chip (NoC) architectures is presented in this paper.  ...  However, several different applications are implemented and integrated in the modern complex system-on-chips which should be considered by mapping methods.  ...  The topologies proposed for on-chip networks vary from regular tiled-based [5] , [6] to fully customized structures [7] , [10] , [11] .  ... 
doi:10.1109/iccd.2007.4601933 dblp:conf/iccd/ModarressiS07 fatcat:xy7nuvnbajcylggwdtcl6gtgk4

Special issue of International Journal of Electronics on evolutionary synthesis of network-on-chip-based systems

N. Nedjah, A. H. Bouchachia, L. M. Mourelle
2010 International journal of electronics (Print)  
Network-on-chip (NoC) is an emerging paradigm for communications within large very-large-scale integrated (VLSI) systems implemented on a single silicon chip.  ...  In the fifth paper, entitled 'A high performance, low area reconfiguration controller for network-on-chip-based partial dynamically reconfigurable SoC designs', the authors propose a high-performance yet  ... 
doi:10.1080/00207217.2010.514128 fatcat:26o4i4rrlzgqvcpeqo6jjmb3ky

SMART: A Single-Cycle Reconfigurable NoC for SoC Applications

Chia-Hsin Owen Chen, Sunghyun Park, Tushar Krishna, Suvinay Subramanian, Anantha P. Chandrakasan, Li-Shiuan Peh
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013  
In this paper, we propose Single-cycle Multihop Asynchronous Repeated Traversal (SMART) NoC, a NoC that reconfigures and tailors a generic mesh topology for SoC applications at runtime.  ...  As technology scales, SoCs are increasing in core counts, leading to the need for scalable NoCs to interconnect the multiple cores on the chip.  ...  ACKNOWLEDGEMENT The authers acknowledge the support of DARPA under the Ubiquitous High-Performance Computing (UHPC) program, and Michel Kinsy from MIT for providing H264 task graph.  ... 
doi:10.7873/date.2013.080 dblp:conf/date/ChenPKSCP13 fatcat:lrjfa2wboba2nnj2br5rsnt3jq

A Survey on Reconfigurable System-on-Chips

Hung Kiem Nguyen, Tu Xuan Tran
2018 REV Journal on Electronics and Communications  
The unique characteristic of such systems is integration of many types of heterogeneous reconfigurable processing fabrics based on a Network-on-Chip.  ...  Afterwards, the key issues of designing the reconfigurable SoCs are discussed, with the focus on the challenges when designing reconfigurable hardware fabrics and reconfigurable Network-on-Chips.  ...  Cyberphysical system-on-chip (CPSoC) Cyberphysical System-on-Chip (CPSoC) is an embedded computing platform that achieves self-awareness through a combination of cross-layer sensing, actuation, self-aware  ... 
doi:10.21553/rev-jec.147 fatcat:zqjzktktbjh4los7luipp45cvy

On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems

Lei Zhang, Yinhe Han, Qiang Xu, Xiao wei Li, Huawei Li
2009 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
We then present novel solutions for the above problem, which not only maximize the performance of the on-chip communication scheme, but also provide a unified topology to Operating System and application  ...  Homogeneous manycore systems are emerging for tera-scale computation and typically utilize Network-on-Chip (NoC) as the communication scheme between embedded cores.  ...  ACKNOWLEDGMENT The authors would like to thank the anonymous reviewers for their constructive comments.  ... 
doi:10.1109/tvlsi.2008.2002108 fatcat:hlh257nyynek3erogi5bqd2v4m

Hungarian algorithm based virtualization to maintain application timing similarity for defect-tolerant NoC

Ke Yue, Frank Lockom, Zheng Li, Soumia Ghalim, Shangping Ren, Lei Zhang, Xiaowei Li
2012 17th Asia and South Pacific Design Automation Conference  
Typically, these processors employ Network-on-Chip (NoC) as the communication infrastructure and core-level redundancy is often used as an effective approach to improve the yield of manycore chips.  ...  Based on this metric, a Hungarian method based algorithm is developed to reconfigure a defect-tolerant manycore platform and form a unified application specific virtual core topology of which the timing  ...  Different from the prior work listed above, we focus on topology reconfiguration for applications with timing con-straints.  ... 
doi:10.1109/aspdac.2012.6165003 dblp:conf/aspdac/YueLLGRZL12 fatcat:a5orhxker5aibb52bjpr4ofpjy

An Overview of Efficient Interconnection Networks for Deep Neural Network Accelerators

Seyed Morteza Nabavinejad, Mohammad Baharloo, Kun-Chih Chen, Maurizio Palesi, Tim Kogel, Masoumeh Ebrahimi
2020 IEEE Journal on Emerging and Selected Topics in Circuits and Systems  
With this motivation, reconfigurable DNN computing with flexible on-chip interconnection will be investigated in this paper.  ...  As a result, efficient interconnection and data movement mechanisms for future on-chip artificial intelligence (AI) accelerators are worthy of study.  ...  In summary, a proper on-chip interconnection for the DNN operations depends on the target applications and design goals.  ... 
doi:10.1109/jetcas.2020.3022920 fatcat:idqitgwnrnegbd4dhrly3xsxbi

A reconfigurable fault-tolerant deflection routing algorithm based on reinforcement learning for network-on-chip

Chaochao Feng, Zhonghai Lu, Axel Jantsch, Jinwen Li, Minxuan Zhang
2010 Proceedings of the Third International Workshop on Network on Chip Architectures - NoCArc '10  
Zhang et al. " A reconfigurable routing algorithm for a faulttolerant 2D-mesh Network-on-Chip" , DAC'08  Deterministic, fault-tolerant, distributed, reconfigurable routing algorithm to handle one faulty  ...  Zhang et al. " A reconfigurable routing algorithm for a fault- Z.  ...  FoN: Fault-on-Neighbor aware routing algorithm for Networks-on-Chip . SOCC' 10  ... 
doi:10.1145/1921249.1921254 dblp:conf/micro/FengLJLZ10 fatcat:j3sggbfz3rbe5kofondlq2kvjq

Skip-links: A dynamically reconfiguring topology for energy-efficient NoCs

Chris Jackson, Simon J. Hollis
2010 2010 International Symposium on System on Chip  
We introduce the Skip-link architecture that dynamically reconfigures Network-on-Chip (NoC) topologies, in order to reduce the overall switching activity in many-core systems.  ...  Our architecture monitors traffic behaviour and optimises the mesh topology without prior analysis of communications behaviour, and is thus applicable to all applications.  ...  In [6, Sect. 4.3] the shortcomings of fixed-topology on-chip interconnects are discussed and it is suggested that many applications have communication patterns for which an optimal topology can be configured  ... 
doi:10.1109/issoc.2010.5625537 dblp:conf/issoc/JacksonH10 fatcat:3rg2v5vgrzb45jyiycoeib6ebe

FASHION: Fault-Aware Self-Healing Intelligent On-chip Network [article]

Pengju Ren, Michel A.Kinsy, Mengjiao Zhu, Shreeya Khadka, Mihailo Isakov, Aniruddh Ramrakhyani, Tushar Krishna, Nanning Zheng
2017 arXiv   pre-print
In this work, we introduce the Fashion router, a self-monitoring and self-reconfiguring design that allows for the on-chip network to dynamically adapt to component failures.  ...  The Fashion router places no restriction on topology, position or number of faults.  ...  Fig. 2 . 2 Fashion: Fault-Aware Self-Healing Intelligent On-chip Network router. Fig. 3 . 3 k1depth, k2depth...) k1,k2...  ... 
arXiv:1702.02313v1 fatcat:jq4yi2smbjf6foqmxuvabqslue

Cardio: Adaptive CMPs for reliability through dynamic introspective operation

Andrea Pellegrini, Valeria Bertacco
2011 2011 IEEE International High Level Design Validation and Test Workshop  
In this work, we propose Cardio, a distributed architecture for reliable chip multiprocessors.  ...  Cardio, a novel approach for onchip reliability is based on hardware detectors that spot failures and on software routines that reorganize the system to work around faulty components.  ...  We evaluated Cardio on a custom, fault-aware simulator for chip multiprocessors and studied the dynamic capability of Cardio to overcome permanent faults, showing that its reconfiguration time is comprised  ... 
doi:10.1109/hldvt.2011.6113983 dblp:conf/hldvt/PellegriniB11 fatcat:tshn2j45prc3hpovyuvrbcbihm
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