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Benchmarking of Neuromorphic Hardware Systems

Christoph Ostrau, Christian Klarhorst, Michael Thies, Ulrich Rückert
2020 Proceedings of the Neuro-inspired Computational Elements Workshop  
With more and more neuromorphic hardware systems for the acceleration of spiking neural networks available in science and industry, there is a demand for platform comparison and performance estimation  ...  CCS CONCEPTS • Hardware → Power and energy; • Computing methodologies → Neural networks.  ...  In this approach, we take a user's perspective and use the same network description on every hardware platform (compare Figure 1 ).  ... 
doi:10.1145/3381755.3381772 dblp:conf/nice/OstrauKT020 fatcat:zs5jip3e5jejlczvxib3pe7hd4

On the impact of dynamic data management for distributed local memories in heterogeneous MPSoCs

Benedikt Noethen, Oliver Arnold, Gerhard Fettweis
2013 2013 International Symposium on System on Chip (SoC)  
Furthermore, the available on-chip memory is not efficiently utilized according to the application requirements.  ...  Hence data locality and system performance is improved. This strategy leads to a dramatic reduction in the number of accesses to the external memory for data-intensive applications.  ...  Furthermore, we would like to thank Synopsys, Tensilica and Xilinx for sponsoring Software, IPs and prototyping FPGAs.  ... 
doi:10.1109/issoc.2013.6675267 dblp:conf/issoc/NoethenAF13 fatcat:yzyxudg2tra6lpfigirjnm42w4

High-Performance Embedded Architecture and Compilation Roadmap [chapter]

Koen De Bosschere, Wayne Luk, Xavier Martorell, Nacho Navarro, Mike O'Boyle, Dionisios Pnevmatikatos, Alex Ramirez, Pascal Sainrat, André Seznec, Per Stenström, Olivier Temam
2007 Lecture Notes in Computer Science  
One of the key deliverables of the EU HiPEAC FP6 Network of Excellence is a roadmap on high-performance embedded architecture and compilation -the HiPEAC Roadmap for short.  ...  (vi) runtime systems, (vii) benchmarking, (viii) simulation and system modeling, (ix) reconfigurable computing, and (x) real-time systems.  ...  network-on-chip (NoC) technologies.  ... 
doi:10.1007/978-3-540-71528-3_2 fatcat:ywmebvj7wrfb3ojghsjs4w3fy4

Developing architectural platforms: a disciplined approach

A. Mihal, C. Kulkarni, M. Moskewicz, M. Tsai, N. Shah, S. Weber, Yujia Jin, K. Keutzer, K. Vissers, C. Sauer, S. Malik
2002 IEEE Design & Test of Computers  
On-chip communication modeling Communication architecture design in Teepee is based on the network-on-a-chip paradigm. 11 Teepee's multiprocessor view portrays the system architecture at the coarsest  ...  Architects construct network topologies using an extendable library of network-on-a-chip components.  ... 
doi:10.1109/mdt.2002.1047739 fatcat:3od3meg5gbaabdlflfycfb2cy4

Towards Open Network-on-Chip Benchmarks

Cristian Grecu, Andre Ivanov, Partha Pande, Axel Jantsch, Erno Salminen, Umit Ogras, Radu Marculescu
2007 First International Symposium on Networks-on-Chip (NOCS'07)  
This document outlines the top-level view on a system of benchmarks for Networks on Chip (NoC), which intends to cover a wide spectrum of NoC design aspects, from application modeling to performance evaluation  ...  For performance benchmarking, requirements and features are described for application programs, synthetic micro-benchmarks, and abstract benchmark applications.  ...  Acknowledgements The authors would like to thank OCP-IP for its continued support and contribution.  ... 
doi:10.1109/nocs.2007.44 dblp:conf/nocs/GrecuIPJSOM07 fatcat:a3kxtrpoxfg6vosazwbxshznge

A comprehensive workflow for general-purpose neural modeling with highly configurable neuromorphic hardware systems

Daniel Brüderle, Mihai A. Petrovici, Bernhard Vogginger, Matthias Ehrlich, Thomas Pfeil, Sebastian Millner, Andreas Grübl, Karsten Wendt, Eric Müller, Marc-Olivier Schwartz, Dan Husmann de Oliveira, Sebastian Jeltsch (+22 others)
2011 Biological cybernetics  
The integration of these components into one hardware-software workflow provides an ecosystem for ongoing preparative studies that support the hardware design process and represents the basis for the maturity  ...  integration of the hardware interface into the simulator-independent model description language PyNN; a fully automated translation between the PyNN domain and appropriate hardware configurations; an executable  ...  hand and the usability and spectrum of possible applications for modelers without a hardware background on the other.  ... 
doi:10.1007/s00422-011-0435-9 pmid:21618053 fatcat:qeziz4fw4zgk5eqnohmgunuyqy

Exploration of Distributed Shared Memory Architectures for NoC-based Multiprocessors

Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa
2006 2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation  
Multiprocessor system-on-chip (MP-SoC) platforms represent an emerging trend for embedded multimedia applications.  ...  Experimental results show the impact of different NoC topologies and distributed shared memory configurations for a selected set of parallel benchmark applications from the power/performance perspective  ...  For this purpose, a distributed shared memory architecture has been proposed, that is suitable for low-power on-chip multiprocessors and supported by an on-chip hardware MMU.  ... 
doi:10.1109/icsamos.2006.300821 dblp:conf/samos/MonchieroPSV06 fatcat:cu6537637na4vgk3bfthdjxuoe

Simulation of a digital neuro-chip for spiking neural networks

T. Schoenauer, S. Atasoy, N. Mehrtash, H. Klar
2000 Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks. IJCNN 2000. Neural Computing: New Challenges and Perspectives for the New Millennium  
We present the hardware structure of the NeuroPipe-Chip, which is modelled on register-transfer-level (RTL) using the hardware description language VHDL.  ...  For a simple SNN for image segmentation, the NeuroPipe-Chip operating at 100MHz shows an improvement of more than two orders of magnitude compared to an Alpha 500MHz workstation and approaches real-time  ...  In the process of designing the NeuroPipe-Chip, we realized a RTL-Model of the chip in the hardware description language VHDL.  ... 
doi:10.1109/ijcnn.2000.860819 dblp:conf/ijcnn/SchoenauerAMK00 fatcat:sazbac72oncspeu2j5cdkz5c3a

WASHINGTON STATE UNIVERSITY

1968 Anthropology News  
This document outlines the top-level view on a system of benchmarks for Networks on Chip (NoC), which intends to cover a wide spectrum of NoC design aspects, from application modeling to performance evaluation  ...  For performance benchmarking, requirements and features are described for application programs, synthetic micro-benchmarks, and abstract benchmark applications.  ...  Acknowledgements The authors would like to thank OCP-IP for its continued support and contribution.  ... 
doi:10.1111/an.1968.9.2.5.1 fatcat:x3stlwwlsjgcheeirzuk4clxoe

WASHINGTON STATE UNIVERSITY

1968 Anthropology News  
This document outlines the top-level view on a system of benchmarks for Networks on Chip (NoC), which intends to cover a wide spectrum of NoC design aspects, from application modeling to performance evaluation  ...  For performance benchmarking, requirements and features are described for application programs, synthetic micro-benchmarks, and abstract benchmark applications.  ...  Acknowledgements The authors would like to thank OCP-IP for its continued support and contribution.  ... 
doi:10.1111/an.1968.9.3.9.1 fatcat:a3yjy2jdk5ecfeq5zdruh6luqm

TRIM: A Design Space Exploration Model for Deep Neural Networks Inference and Training Accelerators [article]

Yangjie Qi, Shuo Zhang, Tarek M. Taha
2022 arXiv   pre-print
There is increasing demand for specialized hardware for training deep neural networks, both in edge/IoT environments and in high-performance computing systems.  ...  The model evaluates at the whole network level, considering both inter-layer and intra-layer activities.  ...  Task Description The task description used in our paper is a simplified TensorFlow-like description, which consists of the network parameters and network model, so it should be easy for Tensor-Flow users  ... 
arXiv:2105.08239v3 fatcat:ullymz35ibgl5df6mjteudyhoy

NeuroPipe-Chip: A digital neuro-processor for spiking neural networks

T. Schoenauer, S. Atasoy, N. Mehrtash, H. Klar
2002 IEEE Transactions on Neural Networks  
We present the hardware structure of the prototype and evaluate its performance in a system simulation based on a hardware description language (HDL).  ...  Computing complex spiking artificial neural networks (SANNs) on conventional hardware platforms is far from reaching real-time requirements.  ...  Voss during chip testing.  ... 
doi:10.1109/72.977304 pmid:18244419 fatcat:gvrygs5t5fhznbur3zmpdct3ry

Exploration of distributed shared memory architectures for NoC-based multiprocessors

Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa
2007 Journal of systems architecture  
Multiprocessor system-on-chip (MP-SoC) platforms represent an emerging trend for embedded multimedia applications.  ...  Experimental results show the impact of different NoC topologies and distributed shared memory configurations for a selected set of parallel benchmark applications from the power/performance perspective  ...  For this purpose, a distributed shared memory architecture has been proposed, that is suitable for low-power on-chip multiprocessors and supported by an on-chip hardware MMU.  ... 
doi:10.1016/j.sysarc.2007.01.008 fatcat:6jjvd42x2vetdmai3ftipxlg5e

Machine Learning Application Benchmark for Satellite On-Board Data Processing

Max Ghiglione, Amir Raoofy, Gabriel Dax, Gianluca Furano, Richard Wiest, Carsten Trinitis, Martin Werner, Martin Schulz, Martin Langer
2021 Zenodo  
The challenge of implementing such ML applications lies mainly on three points: 1) There are limited processing capabilities on spacecraft hardware, meaning that algorithms need to be optimized for their  ...  In this work, we specifically focus on the description of this benchmark as the main part of MLAB project, and discuss initial findings and directions with respect to the datasets and tools.  ...  ACKNOWLEDGEMENTS The authors would like to acknowledge the support and guidance provided by the ESA technical officer Gianluca Furano under the scope of the MLAB contract.  ... 
doi:10.5281/zenodo.5520876 fatcat:uumnhdvibff6vgoo4vxipheoxu

Automatic Generation of Efficient Accelerators for Reconfigurable Hardware

David Koeplinger, Raghu Prabhakar, Yaqi Zhang, Christina Delimitrou, Christos Kozyrakis, Kunle Olukotun
2016 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA)  
We describe a hybrid area estimation technique which uses template-level models and design-level artificial neural networks to account for effects from hardware place-and-route tools, including routing  ...  Our runtime estimation accounts for off-chip memory accesses.  ...  ACKNOWLEDGMENTS The authors thank Maxeler Technologies for their assistance with this paper, and the reviewers for their suggestions.  ... 
doi:10.1109/isca.2016.20 dblp:conf/isca/KoeplingerPZDKO16 fatcat:wxo2ezckinb37lgkyek2lt4c2q
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