A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
Filters
Analyzing specifications for delay-insensitive circuits
Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems
Preserved Fulltext
We present the XDI Model for specifying delay-insensitive circuits, that is, reactive systems that correctly exchange signals with their environment in spite of unknown delays incurred by the interface ...
Abstract We present the XDI Model for specifying delayinsensitive circuits, that is, reactive systems that correctly exchange signals with their environment in spite of unknown delays incurred by the interface ...
Acknowledgments I would like to thank Rudolf Mak for valuable comments on this paper. I also appreciated the many detailed suggestions provided by the anonymous reviewers. ...
doi:10.1109/async.1998.666503
dblp:conf/async/Verhoeff98
fatcat:cnqe5q5gpfh6vgrt3g6yjm3uoq
Building Asynchronous Circuits with JBits
[chapter]
2001
Lecture Notes in Computer Science
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
The design of the circuit is described as well as modifications to the design tools to simplify asynchronous circuit specification. ...
Because of the control given to the user, the JBits API is an ideal design environment for implementing asynchronous circuits on mainstream FPGAs. ...
In most cases the circuit can be considered delay insensitive. To analyze the timing constraints, only partial circuits must be analyzed. ...
doi:10.1007/3-540-44687-7_68
fatcat:y5j7frbggrff5hh5opifg4cozu
A formal model for defining and classifying delay-insensitive circuits and systems
1986
Distributed computing
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
Louis, possible, where I became familiar with delay-insensitive systems and benefited a lot from the approach towards delay-insensitivity that had been established already in his group. ...
Especially the insight that a specification pertains symmetrically to mechanism and environment was very helpful. ...
Trace theory In order to define and classify delay-insensitive circuits we need a formalism for their specification. ...
doi:10.1007/bf01660032
fatcat:bz3staok2febdi57r6uhvabvru
A design methodology for temperature variation insensitive low power circuits
2006
Proceedings of the 16th ACM Great Lakes symposium on VLSI - GLSVLSI '06
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
The energy, delay, and energy-delay product (EDP) are compared at the supply voltages that yield temperature variation insensitive circuit performance and minimum energy-delay product. ...
A design methodology based on optimizing the supply voltage for temperature variation insensitive circuit performance is presented in this paper. ...
The delay, energy-delay product, and delay variations for circuits operating at the nominal supply voltage, supply voltage for temperature variation insensitive delay, and the supply voltage for minimum ...
doi:10.1145/1127908.1128002
dblp:conf/glvlsi/KumarK06
fatcat:k4pljnpdlvgvdj726mq7cjo5zu
Modeling and design of asynchronous priority arbiters for on-chip communication systems
[chapter]
2002
IFIP Advances in Information and Communication Technology
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2019; you can also visit the original URL.
The file type is application/pdf.
The paper focuses on high-level modeling and delay-insensitive implementations of fixed and dynamic priority arbiter. ...
Clock-less, delay-insensitive arbiters are studied in the perspective of making easier and more practical the design of future GALS or GALA SoCs. ...
Delay-insensitive gate-level implementations are derived from the CHP specifications following a method that is not fully automated so far. ...
doi:10.1007/978-0-387-35597-9_27
fatcat:oqowulqvsrft7otpmu7vxj4xni
Qualifying Relative Timing Constraints for Asynchronous Circuits
2016
2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
The paper applies the methodology and tool to optimize the extraction of relative timing constraints for delay insensitive timing models of asynchronous circuits. ...
Relative Timing uses path based timing constraints to guarantee that a circuit conforms to its behavioral specification. ...
The analysis is then incorporated into a tool to optimize the generation of RT constraints for delay-insensitive (DI) circuit models. ...
doi:10.1109/async.2016.23
dblp:conf/async/ManoranjanS16
fatcat:vhbok2k5ifecfamzg7bknby4y4
Eliminating isochronic-fork constraints in quasi-delay-insensitive circuits
2001
Proceedings of the 2001 conference on Asia South Pacific design automation - ASP-DAC '01
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
The Quasi-Delay-Insensitive (QDI) model assumes that all the forks are isochronic. ...
QDI circuits do not actually have to be "isochronic"or can be even ignored. ...
Introduction Delay-insensitive (DI) circuits are a class of asynchronous circuits whose correct operation is independent of any delays in gates and wires. ...
doi:10.1145/370155.370450
dblp:conf/aspdac/SretasereekulN01
fatcat:3ksslnrmvbhznlr6fr6jz7ifja
Design of asynchronous circuits using synchronous CAD tools
2002
IEEE Design & Test of Computers
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2018; you can also visit the original URL.
The file type is application/pdf.
A new design flow, NCL_X, based entirely on commercial CAD tools, targets a subclass of asynchronous circuits called null convention logic. ...
NCL_X shows significant area improvement over other flows for this subclass. Request Register A Request Register B Completion detector Completion detector Combinational logic Ack_a Ack_b Figure 3. ...
Acknowledgments We thank Karl Fant, Michiel Ligthart, Ross Smith, and Alexander Taubin for their invaluable help in discussing and implementing the NCL_X design flow. ...
doi:10.1109/mdt.2002.1018139
fatcat:6dogthchtjeozgzso7cxqpc5wm
Synthesis of PCHB-WCHB hybrid quasi-delay insensitive circuits
2014
2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
Among various techniques, quasi-delay-insensitive (QDI) design is promising due to its very relaxed timing assumption. ...
To overcome this obstacle, this paper proposes an efficient static performance analysis procedure and a synthesis flow for precharged half buffer (PCHB) and weak-conditioned half buffer (WCHB) circuit ...
Quasi-Delay Insensitive Model The delay insensitive (DI) model makes no timing assumption on the gate and wire delays in a circuit, and is the most robust delay model in asynchronous design. ...
doi:10.1109/dac.2014.6881519
fatcat:pcylsvl7irbozm32chbnz7kqja
Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits
2014
Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference - DAC '14
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
Among various techniques, quasi-delay-insensitive (QDI) design is promising due to its very relaxed timing assumption. ...
To overcome this obstacle, this paper proposes an efficient static performance analysis procedure and a synthesis flow for precharged half buffer (PCHB) and weak-conditioned half buffer (WCHB) circuit ...
Quasi-Delay Insensitive Model The delay insensitive (DI) model makes no timing assumption on the gate and wire delays in a circuit, and is the most robust delay model in asynchronous design. ...
doi:10.1145/2593069.2593224
dblp:conf/dac/ChuangLJ14
fatcat:uafzc2vcffh53geaqy7deioalm
Dual-Threshold Voltage Technique for Asynchronous Pre-Charge Full Buffer Linear-Pipelines
2007
2007 6th IEEE Dallas Circuits and Systems Workshop on System-on-Chip
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
In order to reduce leakage power an algorithm for assigning a high threshold voltage is proposed. ...
Scaling the technology and reducing the feature size in integrated circuits have caused leakage power consumption to become one of the main challenges to the digital design. ...
An asynchronous circuit is called delay-insensitive (DI) if it preserves its functionality, independent of the delays of gates and wires [5] . ...
doi:10.1109/dcas.2007.4433218
fatcat:v6ilktzuqbdozjiqyivul7ddke
Design and Validation of Low-Power Secure and Dependable Elliptic Curve Cryptosystem
2021
Journal of Low Power Electronics and Applications
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2022; you can also visit the original URL.
The file type is application/pdf.
We transform this circuit into a multi-threshold dual-spacer dual-rail delay-insensitive logic (MTD3L) circuit. We then design point-addition and point-doubling circuits using the same procedure. ...
In this work, we design a robust asynchronous circuit for scalar multiplication that is resistant to state-of-the-art timing, power, and fault analysis attacks. ...
Designing delay-insensitive asynchronous circuit for scalar multiplication: To design MTD 3 L-based delay-insensitive asynchronous circuits from the combinational circuit generated by our GA (Section 4 ...
doi:10.3390/jlpea11040043
fatcat:witvcqbufjfrfellgkebmjgdqm
Voltage optimization for simultaneous energy efficiency and temperature variation resilience in CMOS circuits
2007
Microelectronics Journal
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
The energy per cycle and the propagation delay at the supply and threshold voltages providing temperature variation insensitive circuit performance, minimum energy-delay product, and minimum energy are ...
A new design methodology based on threshold voltage optimization for achieving temperature variation insensitive circuit speed is also evaluated. ...
As listed in Table 2 , the percent variation in carrier mobility is similar for a specific temperature range at different supply voltages. ...
doi:10.1016/j.mejo.2007.03.011
fatcat:itnjkbyrzbfrfntg7lyzk6blgi
Design, Implementation, and Validation of a New Class of Interface Circuits for Latency-Insensitive Design
2007
2007 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2007)
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2010; you can also visit the original URL.
The file type is application/pdf.
With the arrival of nanometer technologies wire delays are no longer negligible with respect to gate delays, and timing-closure becomes a major challenge to System-on-Chip designers. ...
Latency-insensitive design (LID) has been proposed as a "correct-by-construction" design methodology to cope with this problem. ...
The authors would like to thank Jordi Cortadella for providing the SEA interface circuits and Michael Theobald and Franjo Ivancić for helpful discussions. ...
doi:10.1109/memcod.2007.371256
dblp:conf/memocode/LiCSC07
fatcat:7kxllbop2bebjlexkudthaydz4
Delay Insensitive Ternary CMOS Logic for Secure Hardware
2015
Journal of Low Power Electronics and Applications
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2018; you can also visit the original URL.
The file type is application/pdf.
DITL is compared with other delay insensitive paradigms, such as Pre-Charge Half-Buffers (PCHB) and NULL Convention Logic (NCL) on which it is based. ...
This paper develops the Delay-Insensitive Ternary Logic (DITL) asynchronous design paradigm that combines design aspects of similar dual-rail asynchronous paradigms and Boolean logic to create a single ...
Smith, and Jia Di analyzed the data; Jia Di and Scott C. Smith contributed reagents/materials/analysis tools; Ravi S. P. Nair, Scott C. Smith, and Jia Di wrote the paper. ...
doi:10.3390/jlpea5030183
fatcat:is7pzrncsfgoxa6nacqgju4yeq
« Previous
Showing results 1 — 15 out of 16,018 results