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Performance analysis of location-dependent cache invalidation schemes for mobile environments

Jianliang Xu, Xueyan Tang, Dik Lun Lee
2003 IEEE Transactions on Knowledge and Data Engineering  
This paper considers data inconsistency caused by client movements and proposes three location-dependent cache invalidation schemes.  ...  To the best of the authors' knowledge, previous work on cache invalidation issues focused on data updates only.  ...  The authors would like to thank Tin-Fook Ngai, Qinglong Hu, and the anonymous reviewers for their valuable comments and suggestions that improved the quality of this paper.  ... 
doi:10.1109/tkde.2003.1185846 fatcat:tr6o4akfpfh4fijk66wqshft4u

Tighter WCET analysis of input dependent programs with classified-cache memory architecture

Yanhui Li, Shakith Devinda Fernando, Heng Yu, Xiaolei Chen, Yajun Ha, Teng Tiow Tay
2008 2008 15th IEEE International Conference on Electronics, Circuits and Systems  
Several works have studied the data cache impacts on the WCET of programs, but they can only handle programs with no input dependent data accesses.  ...  Caches in Embedded Systems improve average case performance, but they are a source of unpredictability, especially in the worst case software timing analysis with the consideration of data caches.  ...  for the timing analysis of input-dependent memory accesses.  ... 
doi:10.1109/icecs.2008.4674877 dblp:conf/icecsys/LiFYCHT08 fatcat:b4ou52jjlzhrlngkqucczgtsxy

Exploring Compile Time Caching of Explicit Queries in Programming Codes

Venkata Krishna Suhas Nerella, Sanjay Madria, Thomas Weigert
2012 2012 IEEE 31st Symposium on Reliable Distributed Systems  
We propose determination of cache entries at compile time by performing the program analysis. We also describe the cache heuristics for determining which queries to cache.  ...  This paper presents an approach to reduce the run time execution of programs involving explicit queries by caching the results of repeated queries and incrementally maintaining the cached results.  ...  The primary advantage of performing compile time analysis of query and update patterns is that accurate pattern of query instances and updates in the program will be reflected in the caching pattern of  ... 
doi:10.1109/srds.2012.27 dblp:conf/srds/NerellaMW12 fatcat:i3egd7fqtzfj3akxg6meyx7xry

Associative caches in formal software timing analysis

Fabian Wolf, Jan Staschulat, Rolf Ernst
2002 Proceedings - Design Automation Conference  
Data flow analysis and local simulation of program segments are combined to safely predict cache line contents for associative caches in software running time analysis.  ...  We present an approach that extends instruction and data cache modeling from the granularity of basic blocks to program segments thereby increasing the overall running time analysis precision.  ...  Cache hits or misses depend on the mapping of programs and data to memory, and dependencies can span a whole process or even several process executions.  ... 
doi:10.1145/514074.514076 fatcat:ovcs5ewbwvgg7poxjy7g26konq

Associative caches in formal software timing analysis

F. Wolf, J. Staschulat, R. Ernst
2002 Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)  
Data flow analysis and local simulation of program segments are combined to safely predict cache line contents for associative caches in software running time analysis.  ...  We present an approach that extends instruction and data cache modeling from the granularity of basic blocks to program segments thereby increasing the overall running time analysis precision.  ...  Cache hits or misses depend on the mapping of programs and data to memory, and dependencies can span a whole process or even several process executions.  ... 
doi:10.1109/dac.2002.1012700 fatcat:i5hzbj3ir5bnrcrozpq53v6zxa

Associative caches in formal software timing analysis

Fabian Wolf, Jan Staschulat, Rolf Ernst
2002 Proceedings - Design Automation Conference  
Data flow analysis and local simulation of program segments are combined to safely predict cache line contents for associative caches in software running time analysis.  ...  We present an approach that extends instruction and data cache modeling from the granularity of basic blocks to program segments thereby increasing the overall running time analysis precision.  ...  Cache hits or misses depend on the mapping of programs and data to memory, and dependencies can span a whole process or even several process executions.  ... 
doi:10.1145/513918.514076 dblp:conf/dac/WolfSE02 fatcat:6ayxv3ytnrb4tc5qdmhbuk2mna

Specializing shaders

Brian Guenter, Todd B. Knoblock, Erik Ruf
1995 Proceedings of the 22nd annual conference on Computer graphics and interactive techniques - SIGGRAPH '95  
those computations depending on the parameter being varied; all other values needed by the shader can be precomputed and cached.  ...  We have developed a system for interactive manipulation of shading parameters for three dimensional rendering.  ...  Acknowledgements The authors would like to thank Stephen Coy for the use of his ray tracer and Greg Kusnick, Daniel Ling, Ellen Spertus, and the reviewers for helpful comments on previous drafts of this  ... 
doi:10.1145/218380.218470 dblp:conf/siggraph/GuenterKR95 fatcat:zlqwepija5b77gotodarkvv2ma

A survey of hard real-time scheduling for multiprocessor systems

Robert I. Davis, Alan Burns
2011 ACM Computing Surveys  
Initial papers in this area [10], [14] , [15] , and [16] provide analysis which has complex dependencies on the detailed execution behaviour of contending tasks on other cores.  ...  However, details of the contending tasks may not necessarily be available for analysis, and even if they are, then such cross dependencies go against requirements for composability, which are necessary  ...  Initial papers in this area [10] , [14] , [15] , and [16] provide analysis which has complex dependencies on the detailed execution behaviour of contending tasks on other cores.  ... 
doi:10.1145/1978802.1978814 fatcat:uumyvp23cneobisbkpaogfogci

Shared cache aware task mapping for WCRT minimization

Huping Ding, Yun Liang, T. Mitra
2013 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)  
Thus the mapping of the tasks to the cores should simultaneously maximize workload balance and minimize shared cache interference.  ...  that is agnostic to shared cache conflicts and solely focuses on load balancing.  ...  Acknowledgments This work was supported by Singapore Ministry of Education Academic Research Fund Tier 2 MOE2009-T2-1-033.  ... 
doi:10.1109/aspdac.2013.6509688 dblp:conf/aspdac/DingLM13 fatcat:4avlft3cv5cvxp4nizdliyzbua

Improving worst-case cache performance through selective bypassing and register-indexed cache

Mohamed Ismail, Daniel Lo, G. Edward Suh
2015 Proceedings of the 52nd Annual Design Automation Conference on - DAC '15  
Thus, we explore selectively bypassing caches in order to provide lower WCET. Our experimental results show reductions in WCET of up to 35% over the state-of-the-art static analysis.  ...  In addition, we observe that keeping unpredictable memory accesses in caches can increase or decrease WCET depending on the application.  ...  grant W911NF-11-1-0082, and an equipment donation from Intel.  ... 
doi:10.1145/2744769.2744855 dblp:conf/dac/IsmailLS15 fatcat:y76moji7ojakpfygeov42o4umm

Time-Predictable Computer Architecture

Martin Schoeberl
2009 EURASIP Journal on Embedded Systems  
Features such as pipelines with instruction dependencies, caches, branch prediction, and out-of-order execution complicate WCET analysis and lead to very conservative estimates.  ...  The proposed architecture is evaluated with implementation of some features in a Java processor. The resulting processor is a good target for WCET analysis and still performs well in the average case.  ...  Acknowledgment The author thanks Wolfgang Puffitsch and Florian Brandner for the productive discussions on the topic and suggestions for improving the paper.  ... 
doi:10.1155/2009/758480 fatcat:4mxu4useyngezo5busxvnx3ize

Component-Wise Instruction-Cache Behavior Prediction [chapter]

Abdur Rakib, Oleg Parshin, Stephan Thesing, Reinhard Wilhelm
2004 Lecture Notes in Computer Science  
This proves the correctness of the method based on a previous proof of correctness of the analysis of linked executables. The analysis is described for a general A-way set associative cache.  ...  This paper describes how to perform a component-wise prediction of the instruction-cache behavior guaranteeing conservative results compared to an analysis of a linked executable.  ...  The cache analysis technique works in a bottom-up way starting from minimal modules of the module dependency graph.  ... 
doi:10.1007/978-3-540-30476-0_20 fatcat:wdls2fytn5ayzajlwfliyqbx6m

WCET driven design space exploration of an object cache

Benedikt Huber, Wolfgang Puffitsch, Martin Schoeberl
2010 Proceedings of the 8th International Workshop on Java Technologies for Real-Time and Embedded Systems - JTRES '10  
Depending on the main memory properties (latency and bandwidth), different cache organizations result in the lowest WCET.  ...  We exemplify this approach by a WCET driven design of a cache for heap allocated objects.  ...  Acknowledgements The research leading to these results has received funding from the European Community's Seventh Framework Programme [FP7/2007[FP7/ -2013 under grant agreement number 216682 (JEOPARD) and  ... 
doi:10.1145/1850771.1850775 dblp:conf/jtres/HuberPS10 fatcat:l67ogpx3nbdcjoddbxspag7ds4

Cache analysis in presence of pointer-based data structures

Tomasz Dudziak, Jörg Herter
2011 ACM SIGBED Review  
Cache analysis plays a crucial part when analyzing the WCET of an application.  ...  This paper presents ongoing work aiming at a precise cache analysis in the presence of pointerbased, heap-allocated data structures.  ...  The domain of this analysis phase depends on the number of available cache sets and their associativity (how many memory blocks can be cached per cache set) but is straightforward to implement given the  ... 
doi:10.1145/2038617.2038618 fatcat:vlmx2vvjsbc5dkzucaq47jjwrq

Static timing analysis of embedded software on advanced processor architectures

A. Hergenhan, W. Rosenstiel
2000 Proceedings of the conference on Design, automation and test in Europe - DATE '00  
In detail, the first part of the paper analyzes the connection of prediction accuracy (worst case execution time) and applicability of a methodology for modeling and analysis of instruction as well as  ...  data cache behavior.  ...  Acknowledgments This work is supported in part with funds of the Deutsche Forschungsgemeinschaft (DFG) under reference number 322 1040 within the priority program "Design and design methodology of embedded  ... 
doi:10.1145/343647.343846 fatcat:5ovh4karlvhxtlcklemzbu3d4y
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