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Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices

S. CHO, J.-G. YUN, I. H. PARK, J. H. LEE, J. P. KIM, J.-D. LEE, H. SHIN, B.-G. PARK
2007 IEICE transactions on electronics  
In this study, the dependency of current characteristics on doping profiles is investigated by 3-D numerical analysis.  ...  Through these analyses, the optimum condition of ion implantation for 3-D devices is estimated.  ...  Acknowledgement This work was financially supported by "Tera-bit Level Nano Device Project" of the Korean Ministry of Science and Technology.  ... 
doi:10.1093/ietele/e90-c.5.988 fatcat:ngsv7dcgzrc6lkrihurwrwihly

Recent trends in silicon carbide device research

Munish Vashishath
2008 Maejo International Journal of Science and Technology  
In this paper, silicon carbide Schottky barrier diodes, power MOSFETs, UMOSFET, lateral power MOSFET, SIT (static induction transistor), and nonvolatile memories are discussed along with their characteristics  ...  Because of its wide band gap, the leakage current of SiC is many orders of magnitude lower than that of silicon.  ...  From the characteristics, we can observe the decrease of the drain-current I D at V D > 6 V.  ... 
doaj:b4df4048a4604444812004218b43c7a2 fatcat:kroai575wjdcbdwcahxafhmmcy

Device scaling limits of Si MOSFETs and their application dependencies

D.J. Frank, R.H. Dennard, E. Nowak, P.M. Solomon, Y. Taur, Hon-Sum Philip Wong
2001 Proceedings of the IEEE  
He is currently engaged in the pursuit of sub-one-volt device designs and continues work on high-speed CMOS device design.  ...  , VT, to work on 1-Mb DRAM, and then began work on sub-half-micron MOSFETs for logic in 1984.  ...  Ieong for his work on device modeling, J. Stathis for consultations about oxide reliability, and J. Welser and S. Schuster for useful discussions. The authors would also like to thank Y. Naveh and K.  ... 
doi:10.1109/5.915374 fatcat:r4tvpqmqofgrfg2zuxhrtjwpqe

2020 Index IEEE Transactions on Electron Devices Vol. 67

2020 IEEE Transactions on Electron Devices  
, Y.S., Modeling of Current Mismatch and 1/f Noise for Halo-Implanted Drain-Extended MOSFETs; 4794-4801 Gupta, C., Gupta, A., Tuli, S., Bury, E., Parvais, B., and Dixit, A., Character-ization and Modeling  ...  , C., A Comprehensive Study of Double-Density Hemi-Cylindrical (HC) 3-D NAND Flash; 5362-5367 Hsu, W., see Liu, H., 1009-1013 Hsu, W., see Huang, Y., TED Dec. 2020 5434-5440 Hsueh, F., see Sung, P.  ...  ., +, TED March 2020 1059-1065 AC-SSRM 2-D Cross-Sectional Doping Profiling for DRAM Access Devices Contact Implants.  ... 
doi:10.1109/ted.2021.3054448 fatcat:r4ertn5jordkfjjvorvss7n6ju

Electronics Below 10 nm [chapter]

Konstantin Likharev
2003 Nano and Giga Challenges in Microelectronics  
These devices would be fabricated by chemically-assisted self-assembly from solution on few-nm-pitch nanowire arrays connecting them to the CMOS stack.  ...  as well as new concepts for nanometer-scalable memory cells.  ...  For sub-10-nm devices the volume V of these regions is of the order of 0.3×10 -18 cm 3 ; hence to keep device-to-device fluctuations below 10% the doping rate N/V should be at least as high as 3×10 20  ... 
doi:10.1016/b978-044451494-3/50002-0 fatcat:mnnrwqks5bekpb2kcqo3tcbxzu

Nanoscale CMOS

H.-S.P. Wong, D.J. Frank, P.M. Solomon, C.H.J. Wann, J.J. Welser
1999 Proceedings of the IEEE  
Watson Research Center, and his current research activities focus on novel silicon devices, including vertical transistors and nanostructures, for a variety of memory applications.  ...  Solomon is a member of APS. on GaAs devices, and a postdoctoral position at Stanford University (1995), where he continued his thesis research on SiGe materials and their applications to MOSFET devices  ...  ACKNOWLEDGMENT The authors would like to acknowledge the contributions of the Silicon Innovation Laboratory for fabricating the devices described in this paper.  ... 
doi:10.1109/5.752515 fatcat:siz3jry7hjctlkjesyr5s6vh2m

A simple subcircuit extension of the BSIM3v3 model for CMOS RF design

Suet Fong Tin, A.A. Osman, K. Mayaram, Chenming Hu
2000 IEEE Journal of Solid-State Circuits  
An accurate and simple lumped-element extension of the BSIM3v3 MOSFET model for small-signal radio-frequency circuit simulation is proposed and investigated.  ...  Detailed comparisons of the small-signal and parameters with both two-dimensional device simulations and measurement data are presented.  ...  Jing for several helpful discussions and Avant! TMA for providing the device simulation tools. X. Ouyang's help with the low-frequency measurements and P.  ... 
doi:10.1109/4.839921 fatcat:6rghkwvywzgsno6znqlsei2pgy

Core-Shell Dual-Gate Nanowire Memory as a Synaptic Device for Neuromorphic Application

Md. Hasan Raza Ansari, Seongjae Cho, Jong-Ho Lee, Byung-Gook Park
2021 IEEE Journal of the Electron Devices Society  
In this work, a synaptic device for neuromorphic system is proposed and designed to emulate the biological behaviors in the novel device structure of core-shell dual-gate (CSDG) nanowire flash memory.  ...  The proposed device shows a stronger capacitive coupling between the dual gates, which forms a deeper potential well for charge storing and achieves better memory performance metrics such as sensing margin  ...  On the other hand, the synaptic devices based on emerging nonvolatile memories are focused on realization of multiple-weight long-term potentiation in many cases [42] - [46] .  ... 
doi:10.1109/jeds.2021.3111343 fatcat:jn2zjzut75cbjb4ilisk5ew2ge

Bipolar spintronics: from spin injection to spin-controlled logic

Igor Žutić, Jaroslav Fabian, Steven C Erwin
2007 Journal of Physics: Condensed Matter  
memory devices, is not sufficient for signal processing and digital logic.  ...  current-voltage characteristics to implement spin-based logic.  ...  Ridge National Laboratory, which is supported by the Office of Science of the US Department of Energy under contract No DE-AC05-00OR22725.  ... 
doi:10.1088/0953-8984/19/16/165219 fatcat:b6opalb7inecfpnzabe2d6rq3u

Access devices for 3D crosspoint memory

Geoffrey W. Burr, Rohit S. Shenoy, Kumar Virwani, Pritish Narayanan, Alvaro Padilla, Bülent Kurdi, Hyunsang Hwang
2014 Journal of Vacuum Science and Technology B:Nanotechnology and Microelectronics  
Finally, the authors discuss various approaches for self-selected nonvolatile memories based on Resistive RAM.  ...  The emergence of new nonvolatile memory (NVM) technologies-such as phase change memory, resistive, and spin-torque-transfer magnetic RAM-has been motivated by exciting applications such as storage class  ...  [50] [51] [52] The basic idea (Fig. 3) is to establish a NPN doping profile that results in the formation of a potential barrier for electron transport from one side of the device to the other at  ... 
doi:10.1116/1.4889999 fatcat:oa2vb33xp5dbvaqrw6efyimdzm

Ultra-thin ferroelectrics

Huimin Qiao, Chenxi Wang, Woo Seok Choi, Min Hyuk Park, Yunseok Kim
2021 Materials science & engineering. R, Reports  
Further, we discuss the characterization techniques used to verify the ultra-thin limit of ferroelectricity, followed by device applications based on various emergent properties of ultra-thin ferroelectrics  ...  Later studies reported that ferroelectricity of BTO survives down to ~2 nm ( Fig. 9(d) and (e)) by decreasing the temperature, consistent with the prediction by Junquera and Ghosez [7, 35, 137] .  ...  CMOS-based neuromorphic computing systems are currently more intensively studied than hardware-based systems based on nonvolatile memory devices.  ... 
doi:10.1016/j.mser.2021.100622 fatcat:473vmnu4vjbwxc7v644zt2sdci

Correlated Electron Materials and Field Effect Transistors for Logic: A Review

You Zhou, Shriram Ramanathan
2013 Critical reviews in solid state and materials sciences  
Recent efforts have been focused on electrostatic doping of such materials to probe the underlying physics without introducing disorder as well as to build field-effect transistors that may complement  ...  The review concludes with a brief discussion on the prospects and suggestions for future research directions in correlated oxide electronics for information processing.  ...  Also the expected nonvolatile carrier density modulation may decrease the stand-by power and be utilized in memory applications.  ... 
doi:10.1080/10408436.2012.719131 fatcat:p6rc323pxvcyximoog4i74egfm

Recent Advances in Electronic and Optoelectronic Devices Based on Two-Dimensional Transition Metal Dichalcogenides

2017 Electronics  
The mobility is determined by the combined effect of the homopolar phonon and the polar-optical phonon scatterings at room temperature [46] .  ...  Electronics 2017, 6, 43 2 of 40 review on the same topics [9] . For the convenience of the readers, we summarize a series of TMDCs along with the nature of their band gaps in Table 1 .  ...  The founding sponsors had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript; or in the decision to publish the results.  ... 
doi:10.3390/electronics6020043 fatcat:oaq4mpu6wfbghonfhq4kef76ki

Recent progress in low-temperature-process monolithic three dimension technology

Chih-Chao Yang, Tung-Ying Hsieh, Wen-Hsien Huang, Chang-Hong Shen, Jia-Min Shieh, Wen-Kuan Yeh, Meng-Chyi Wu
2018 Japanese Journal of Applied Physics  
High-performance poly-Ge short-channel metal-oxide-semiconductor field-effect transistors formed on SiO 2 layer by flash lamp annealing Koji Usuda, Yoshiki Kamata, Yuuichi Kamimuta et al.  ...  How to manage the thermal impact of multitiered processes, such as dopant activation, source/drain silicidation, and channel formation, and to prevent the degradation of pre-existing devices/circuits become  ...  Acknowledgments The authors would like to thank the Ministry of Science and Technology (MOST 106-2221-E-492-035-) and National Applied Research Laboratories (NARLabs) of the Republic of China for financial  ... 
doi:10.7567/jjap.57.04fa06 fatcat:pdd23clftzb5xf22braavwzzzy

Advanced CMOS Gate Stack: Present Research Progress

Chun Zhao, C. Z. Zhao, M. Werner, S. Taylor, P. R. Chalker
2012 ISRN Nanotechnology  
When the SiO2 gate thickness is reduced below 1.4 nm, electron tunneling effects and high leakage currents occur which present serious obstacles for device reliability.  ...  Following the introduction of HfO2 into the 45 nm process by Intel in 2007, the screening and selection of high-k gate stacks, understanding their properties, and their integration into CMOS technology  ...  A charge trapping memory device using Ti 0.2 Al 0.8 O x film as charge trapping layer and amorphous Al 2 O 3 as the tunneling and blocking layers is fabricated for nonvolatile memory applications [69]  ... 
doi:10.5402/2012/689023 fatcat:xffrpf56ujetzi6hxkpvw3hona
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