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An innovative low-power high-performance programmable signal processor for digital communications

J. H. Moreno, V. Zyuban, U. Shvadron, F. D. Neeser, J. H. Derby, M. S. Ware, K. Kailas, A. Zaks, A. Geva, S. Ben-David, S. W. Asaad, T. W. Fox (+4 others)
2003 IBM Journal of Research and Development  
We describe an innovative low-power high-performance programmable signal processor (DSP) for digital communications.  ...  As a result, the cornerstone of contemporary digital communications are a new generation of digital signal processors characterized by their power efficiency as well as their improved programmability in  ...  The advances resulting from the eLite DSP research has already led to multiple patent applications, and is opening the area of low-power high-performance programmable architectures for DSP applications  ... 
doi:10.1147/rd.472.0299 fatcat:llzoroyazfawpdigtd7wts4usu

A reconfigurable digital signal processing system for eddy currents non-destructive testing

Luis S. Rosado, Pedro M. Ramos, M. Piedade, Telmo G. Santos, P. Vilaca
2010 2010 IEEE Instrumentation & Measurement Technology Conference Proceedings  
The IOnic acquisition card is composed by a programmable gain amplifier and a high speed analog to digital converter.  ...  This paper presents a digital signal processing system specially designed for eddy currents non-destructive testing.  ...  The increasing speed, high flexibility and performance make FPGAs ideal for high data rate digital signal processing.  ... 
doi:10.1109/imtc.2010.5488183 fatcat:3y2wxvclzrggjbwasusrrmaczu

An Overview of Reconfigurable Hardware for Efficient Implementation of DSP Algorithms

Mahesh Kadam
2014 IOSR Journal of Engineering  
Field Programmable Gate Array (FPGA) which finds wide range of applications in the field of signal processing, wireless communication, image and video processing has gained popularity as a reconfigurable  ...  Reconfigurable hardware is emerging as the best option for the efficient implementation of complex and computationally expensive signal processing algorithms.  ...  DSP implementation comparison. [1] Performance Cost Power Flexibility Design effort(NRE) ASIC High High Low Low High Programmable DSP Medium Medium Medium Medium Medium General Purpose  ... 
doi:10.9790/3021-04253443 fatcat:2gl74zcmjjaj7nxi2laq3iu3vm

Using DaVinci Technology for Digital Video Devices

Deepu Talla, Jeremiah Golston
2007 Computer  
the need for high performance, low power, and low system cost.  ...  The extent of programmability, field upgradability, feature future-proofing, and need for universal video decoding or a closed system drive selection of digital signal processors (DSPs), programmable accelerators  ... 
doi:10.1109/mc.2007.366 fatcat:3sm7zuekgvfdrghq7bsokz3p34

A Study on High Performance Embedded Systems with Multiple Processors

Prakash H T, Dr. Srinivas M
2017 IJARCCE  
The progress made in growing more propelled compilers for embedded systems, programming of embedded elite computing systems in light of Digital Signal Processors (DSPs) is as yet an exceedingly talented  ...  In an initial step, low-level programming phrases are distinguished and recouped.  ...  High Performance Digital Signal Processing: Digital Signal Processors (DSPs) are omnipresent and progressively vital in the broadcast communications and hardware industry.  ... 
doi:10.17148/ijarcce.2017.6622 fatcat:zqzlqoep5rbhjjfshxnsw2uaia

Digital Instrumentation for the Radio Astronomy Community [article]

Aaron Parsons, Dan Werthimer, Donald Backer, Tim Bastian, Geoffrey Bower, Walter Brisken, Henry Chen, Adam Deller, Terry Filiba, Dale Gary, Lincoln Greenhill, David Hawkins, Glenn Jones (+10 others)
2009 arXiv   pre-print
Time-to-science is an important figure of merit for digital instrumentation serving the astronomical community.  ...  A digital signal processing (DSP) community is forming that uses shared hardware development, signal processing libraries, and instrument architectures to reduce development time of digital instrumentation  ...  It features an FPGA processor that is programmable with an open-source DSP library, and provides high-bandwidth 10-Gigabit Ethernet interfaces for transmitting and receiving packetized data.  ... 
arXiv:0904.1181v1 fatcat:nr3wgk5nyfd2jbtzguzszjemwe

Radiation Transmission-based Thickness Measurement Systems - Advancements, Innovations and New Technologies [chapter]

Mark E.
2010 Advances in Measurement Systems  
of the measured thickness local to the C-Frame via high speed digital signal processing (DSP) hardware and algorithms • Fully networked, high speed communications for command and status data exchanges  ...  Digital fiber optic communication links were provided to set and monitor the high voltage systems, and to provide inherent isolation to the supervisory and signal processing equipment.  ... 
doi:10.5772/8728 fatcat:cobrah5wxbbazfrb4cawqgqsg4

Digital Automatic Gain Control Integrated On Wlan Platform

Emilija Miletic, Milos Krstic, Maxim Piz, Michael Methfessel
2008 Zenodo  
The control over those signals is performed in our digital baseband processor using dedicated hardware block DAGC.  ...  DAGC function in baseband processor is done in few steps: measuring power levels of baseband samples of an RF signal,accumulating the differences between the measured power level and actual gain setting  ...  On Fig.4 is shown dependency between the input power and RSSI for different LNA setting (LNA high, LNA medium, LNA low).  ... 
doi:10.5281/zenodo.1084837 fatcat:37otl24rfna7jpln3ylote5gaq

Parallel Architecture Core (PAC)—the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Tools

David Chih-Wei Chang, Tay-Jyi Lin, Chung-Ju Wu, Jenq-Kuen Lee, Yuan-Hua Chu, An-Yeu Wu
2010 Journal of Signal Processing Systems  
AVLIW digital signal processor (PACDSP) has been developed from a proprietary instruction set with multimedia-rich instructions, a complexity-effective microarchitecture with an innovative distributed  ...  In order to develop a low-power and highperformance SoC platform for multimedia applications, the Parallel Architecture Core (PAC) project was initiated in Taiwan in 2003.  ...  Digital signal processors (DSP) are programmable processors customized for signal processing, of which the instruction set and the microarchitecture are designed to perform computationintensive tasks efficiently  ... 
doi:10.1007/s11265-010-0470-0 fatcat:3bzqwdxku5aphc5pqmf5iffmya

Smart cameras on a chip: using complementary metal-oxide-semiconductor (CMOS) image sensors to create smart vision chips [chapter]

D. Ginhac
2014 High Performance Silicon Imaging  
High Performance Silicon Imaging Fundamentals and Applications of CMOS and CCD Sensors, Elsevier, pp.  ...  complex algorithms at a high frame rate.  ...  But, for low-level image processing, an analog or a mixed-approach can offer superior performance leading to a smaller, faster, and lower power solution than digital processors (Martin et al. 1998 ).  ... 
doi:10.1533/9780857097521.1.165 fatcat:bkory45dbndwhbkpv6lv2pjbgm

A cellphone for all standards

B. Bing, N. Jayant
2002 IEEE spectrum  
This commercial and military interest in SDR has grown in recent years primarily because high-performance digital signal processors (DSPs) are now available at reasonable prices.  ...  it on to the signal processor for demodulation.  ... 
doi:10.1109/6.999792 fatcat:m3hle6qbbren3kxrvskld23w2q

Highlights of the ISSCC 2013 Processors and High Performance Digital Sessions

Timothy Fischer, Byeong-Gyu Nam, Leland Chang, Tadahiro Kuroda, Michiel A. P. Pertijs
2014 IEEE Journal of Solid-State Circuits  
Highlights of the ISSCC 2013 Processors and High Performance Digital Sessions I.  ...  This January issue includes the topics from the low power and high performance digital, memory, and technology directions as well as imagers, medical and sensors. II.  ... 
doi:10.1109/jssc.2013.2284658 fatcat:5t5rgklrebbafg2lfihlp6qdq4

Trend and Challenge on System-on-a-Chip Designs

Yen-Kuang Chen, S. Y. Kung
2007 Journal of Signal Processing Systems  
For example, recognizing the stringent requirements on power consumption, memory bandwidth/latency, and transistor variability, novel power/thermal management, multi-processor SoC, reconfigurable logic  ...  For example, further innovations on scalable, reusable, and reliable system architectures, IP deployment and integration, on-chip interconnects, and memory hierarchies are all anticipated in the near future  ...  Acknowledgements We would like to thank anonymous reviewers for their constructive comments and suggestions.  ... 
doi:10.1007/s11265-007-0129-7 fatcat:cx7lgcdp4recjnq54pdq2etyyq

Ultra-low power microcontrollers for portable, wearable, and implantable medical electronics

Srinivasa R. Sridhara
2011 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)  
-10uA average power budget for entire system -~2uA average active power budget for digital • Yes, but requires innovation at all levels of SoC design • Rami Abdallah (University of Illinois) • Raul Blazquez  ...  signals tend to have useful information at frequencies less than 1 kHz Ultra-Low Voltage operation • ULV: sub-V t to 2V t • Low-performance applications enable ULV operation -System and micro  ...  and low-voltage operation. • Such ultra-low power operation is a must in enabling advanced signal processing algorithms for the next generation battery-powered medical devices. • The innovative medical  ... 
doi:10.1109/aspdac.2011.5722252 dblp:conf/aspdac/Sridhara11 fatcat:zr5ow6g36feqxh5atxeo5ueceu

Implementatioin of Enhanced Transitional Communication Interface Between Mediums Using Adaptive Techniques

N L Sujatha Chavakula, A. Pravin, S. Kanaka Durga, G. Mallikarjuna
2012 INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY  
Implementation of an innovative and interactive device which is having the capability of changing its own properties with dynamic nature is presented in this project.  ...  It is intended for multi-tasking applications where fully memory management, high performance, and low-power are important.  ...  The Coprocessor interface of ARM926EJ-S processor through CP15 system configuration coprocessor is shown in figure 1 N o v 3 0 , 2 0 1 3 Function of AT89S52 The AT89S52 is a low-power, high-performance  ... 
doi:10.24297/ijct.v11i9.3412 fatcat:utygqbmn7raa5fhlyun6rbnf7e
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