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An improved testing scheme for catastrophic fault patterns

A. Nayak, J. Ren, N. Santoro
2000 Information Processing Letters  
An efficient testing scheme The algorithm The algorithm proceeds as follows. The given fault pattern F is decomposed into patterns which do not contain any gap.  ...  The investigations on the testing problem have been restricted to the particular case of minimal fault patterns (i.e., m = g), and testing schemes have been presented both for unidirectional and for bidirectional  ... 
doi:10.1016/s0020-0190(00)00012-0 fatcat:aznps5nmgzexpainpsy66v77wy

Efficient Unknown Blocking Using LFSR Reseeding

Seongmoon Wang, K.J. Balakrishnan, S.T. Chakradhar
2006 Proceedings of the Design Automation & Test in Europe Conference  
The proposed technique minimizes the size of the LFSR by propagating only one fault effect for each fault and balancing the number of specified bits in each control pattern.  ...  This paper presents an efficient method to block unknown values from entering temporal compactors. The control signals for the blocking logic are generated by an LFSR.  ...  [3] proposed an unknown blocking scheme for Logic BIST based on the above.  ... 
doi:10.1109/date.2006.243929 dblp:conf/date/WangBC06 fatcat:t3lw4imr3jaafeid5mu6uorc6e

Page 6925 of Mathematical Reviews Vol. , Issue 93m [page]

1993 Mathematical Reviews  
The characterization of such patterns of faults is obviously crucial for the identification, testing and detection of catastrophic system events.  ...  We then present an efficient algorithm for constructing a particular fault pattern for unidirectional links, the reference fault pattern, which is at the basis of many applications.  ... 

Page 1906 of Mathematical Reviews Vol. , Issue 97C [page]

1997 Mathematical Reviews  
First, we establish a necessary and sufficient condition for a fault pattern to be catastrophic.  ...  We estimate the minimum number of packets for which there exists an f -fault-tolerant linear broadcast- ing scheme in complete networks, and we construct schemes using few packets.  ... 

A Survey of Testing Techniques for Approximate Integrated Circuits

Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
2020 Proceedings of the IEEE  
Experimental outcomes show that the testing process for AxIC is not completely mature. Indeed, only under specific conditions existing testing procedures achieve good results.  ...  We resort to an illustrative example having the twofold aim of: (i) guiding the reader through the AxIC testing challenges and (ii) illustrating the existing solutions to correctly overcome them, while  ...  Briefly, fault classification has to divide faults into catastrophic (to test) and acceptable (not to test), according to a metric; test pattern generation has to produce tests able to cover all the catastrophic  ... 
doi:10.1109/jproc.2020.2999613 fatcat:xuntqh3kybhyzdkn34yglicf6u

A resistance matching based self-testable current-mode R-2R digital-to-analog converter

Jun Yuan, Masayoshi Tachibana
2013 IEICE Electronics Express  
The circuit-level simulation of the proposed BIST system are presented to demonstrate the feasibility with fault coverage of 96% for R-2R network and 82.6% for the Operational Amplifier (OpAmp), and area  ...  The Built-In Self-Test (BIST) circuits are employed to observe the current redistributions in the resistance matching branches converted from the R-2R network in the DAC, and then the redistributed currents  ...  It was also supported by KAKENHI (23500067) Grant-in-Aid for Scientific Research (C) and the Research Fund (A2013-05) of CQUPT.  ... 
doi:10.1587/elex.10.20130753 fatcat:filsgthydrekngodawfegnhom4

Characterization, testing and reconfiguration of faults in mesh networks

Soumen Maity, Amiya Nayak, S. Ramsundar
2007 Integration  
We determine the minimum number of faults required for a fault pattern to be catastrophic. We consider the problem of testing whether a fault pattern is catastrophic.  ...  The distribution of faults can have several impacts on the effectiveness of any reconfiguration scheme; in fact, patterns of faults occurring at strategic locations may render an entire VLSI system unusable  ...  Thus the problem of testing whether a fault pattern is catastrophic for unidirectional mesh network requires OðN 1 þ N 2 þ wjGjÞ time.  ... 
doi:10.1016/j.vlsi.2006.11.002 fatcat:bk644op6yjer3my5cppyrkrlwu

Improved Winding Mechanical Fault Type Classification Methods Based on Polar Plots and Multiple Support Vector Machines

Jiangnan Liu, Zhongyong Zhao, Kai Pang, Dong Wang, Chao Tang, Chenguo Yao
2020 IEEE Access  
CONCLUSION This paper presents an improved method for classifying and recognizing transformer winding mechanical faults.  ...  Fig. 4 shows the flowchart for training a SVM model. A. IGA-SVM 1) EMPEROR-SELECTIVE (EMS) MATING SCHEME The mating scheme plays an important role in the convergence and robustness of GA.  ... 
doi:10.1109/access.2020.3041298 fatcat:37nboqjypfgjllg32ufjwv2mba

Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs

Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko
2005 Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays - FPGA '05  
It is shown that the low yield predicted for the 45nm technology node and beyond is a cause for concern.  ...  This paper presents an analysis of the potential yield loss in FPGA due to random defects in metal layers.  ...  Figure 1 : 1 Catastrophic faults relative to size.  ... 
doi:10.1145/1046192.1046211 dblp:conf/fpga/CampregherCCV05 fatcat:lx6g2z75l5fmlnsymiljkl2tv4

Expert System for Classification and Analysis of Power System Events

E. Styvaktakis, M. H. J. Bolen, I. Y. H. Gu
2002 IEEE Power Engineering Review  
Incipient fault detection in transformers can provide early warning of electrical failure and could prevent catastrophic losses.  ...  These models were implemented by combining deteriorating insulation models with an internal short-circuit fault model.  ...  This paper presents an artificial neural network (ANN) approach for detection and diagnosis of fault nature and fault location in oil-filled power transformers during impulse testing.  ... 
doi:10.1109/mper.2002.4312021 fatcat:yoi3g5lhs5h5ncmj33fhj5ewxq

Tolerance Towards Sensor Faults: An Application to a Flexible Arm Manipulator

Chee Pin Tan, Maki K. Habib
2006 International Journal of Advanced Robotic Systems  
Excellent results have been obtained for both cases (joint and link); the FTC scheme caused the system performance is almost identical to the fault-free scenario, whilst providing an indication that a  ...  fault is present, even for simultaneous faults.  ...  As such, an FTC scheme can help to reduce the effect of the fault while waiting for the problem to be rectified.  ... 
doi:10.5772/5720 fatcat:jz2ie72lwnh53mix5gjne3kqqu

Yield enhancements of design-specific FPGAs

Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko
2006 Proceedings of the internation symposium on Field programmable gate arrays - FPGA'06  
These parts offer cost reductions by limiting manufacturing tests and improving the number of working devices in a wafer. This paper addresses the issue of yield enhancement in Design-Specific FPGAs.  ...  When combined with existing yield modelling techniques, a quantitative measure of the potential yield improvements of the Design-Specific FPGA approach is reported for current and future technology nodes  ...  ACKNOWLEDGMENTS The authors would like to thank the following people for their helpful discussion relating to this work: Steve Wilton and Robert Isreal of University of British Columbia; Steve Trimberger  ... 
doi:10.1145/1117201.1117215 dblp:conf/fpga/CampregherCCV06 fatcat:xh6bdlppp5h2xltg3xcau3w5la

Unknown Blocking Scheme for Low Control Data Volume and High Observability

Seongmoon Wang, Wenlong Wei, Srimat T. Chakradhar
2007 2007 Design, Automation & Test in Europe Conference & Exhibition  
The proposed method can always achieve the same fault coverage that can be achieved by direct observation of scan chains.  ...  This paper presents a new blocking logic to block unknowns for temporal compactors.  ...  An enhanced channel masking scheme presented in [1] improves observability of the simple channel masking scheme. Naruse et al.  ... 
doi:10.1109/date.2007.364563 dblp:conf/date/WangWC07 fatcat:x7bjjfu5srexpn5lzlt57evo74

A Pattern Recognition Based Method for IC Failure Analysis

A.J. Strojwas, S.W. Director
1985 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
for IC failure analysis has The approach is based on statistical pattern recognition concepts and is especially useful for the detection of parametric faults in monolithic ICs.  ...  For digital ICs. most of the effort has centered around the development of algorithms for automatic test generation. Such techniques are used to detect catastrophic "stuck-at" faults.  ...  In general faults can be classified as either catastrophic or parametric Catastrophic faults are random defects which cause a hard failure of an element in a chip and. consequently, the whole chip fails  ... 
doi:10.1109/tcad.1985.1270100 fatcat:tovv7c4fprde3jmf6cnkuzwyia

A Neural Network-Based Method for Gas Turbine Blading Fault Diagnosis

C. Angelakis, E.N. Loukis, A.D. Pouliezos, G.S. Stavrakakis
2001 International Journal of Modelling and Simulation  
Neural network-based fault diagnosis is treated as a Pattern Recognition problem, based on measurements and feature selection.  ...  Next, in order to improve the generalization capabilities, which are critical for the specific diagnostic problem, a new multinet architecture is developed, based on the idea of "Majority Rule' decision  ...  remaining 9 patterns (1 healthy plus 2 for each fault) was used as the test set for the specific instrument.  ... 
doi:10.1080/02286203.2001.11442186 fatcat:t2kcieqjjrbinn35bl6lxnn4oi
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