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An extensible framework for multicore response time analysis

Robert I. Davis, Sebastian Altmeyer, Leandro S. Indrusiak, Claire Maiza, Vincent Nelis, Jan Reineke
2017 Real-time systems  
An extensible framework for multicore response time analysis Davis, R.I.; Altmeyer, S.J.; Indrusiak, L.S.; Maiza, C.; Nelis, V.; Reineke, J.  ...  Acknowledgements This work was supported in part by the COST Action IC1202 TACLe, by the NWO Veni Project 'The time is now: Timing Verification for Safety-Critical Multi-Cores' by the Deutsche Forschungsgemeinschaft  ...  as part of the project PEP, by National Funds through FCT/MEC (Portuguese Foundation for Science and Technology) and co-financed by ERDF (European Regional Development  ... 
doi:10.1007/s11241-017-9285-4 fatcat:dg6qbbdzfnajxlbsje57ku2ryi

A generic and compositional framework for multicore response time analysis

Sebastian Altmeyer, Robert I. Davis, Leandro Indrusiak, Claire Maiza, Vincent Nelis, Jan Reineke
2015 Proceedings of the 23rd International Conference on Real Time and Networks Systems - RTNS '15  
In this paper, we introduce a Multicore Response Time Analysis (MRTA) framework.  ...  The MRTA framework decouples response time analysis from a reliance on context independent WCET values.  ...  was supported in part by the COST Action IC1202 TACLe, by the DFG as part of the Transregional Collaborative Research Centre SFB/TR 14 (AVACS), by National Funds through FCT/MEC (Portuguese Foundation for  ... 
doi:10.1145/2834848.2834862 dblp:conf/rtns/AltmeyerDIMNR15 fatcat:4ad3vtbawjer7otj44q4dbotqe

Parallelizing Compiler Framework and API for Power Reduction and Software Productivity of Real-Time Heterogeneous Multicores [chapter]

Akihiro Hayashi, Yasutaka Wada, Takeshi Watanabe, Takeshi Sekiguchi, Masayoshi Mase, Jun Shirako, Keiji Kimura, Hironori Kasahara
2011 Lecture Notes in Computer Science  
by a single processor core and 80% of power reduction for the real-time AAC encoding.  ...  The framework attains speedups up to 32x for an optical flow program with eight general purpose processor cores and four DRP(Dynamically Reconfigurable Processor) accelerator cores against sequential execution  ...  Specifications of OSCAR API[6] heterogeneous multicore extension are developed by NEDO Heterogeneous multicore architecture and API committee at Waseda university.  ... 
doi:10.1007/978-3-642-19595-2_13 fatcat:cnrhm5aeszdvfay66rfg3xdsqm

Evaluating industrial applicability of virtualization on a distributed multicore platform

Nesredin Mahmud, Kristian Sandstrom, Aneta Vulgarakis
2014 Proceedings of the 2014 IEEE Emerging Technology and Factory Automation (ETFA)  
However, current advancement in Virtual Machine Monitor, multicore technology, virtualization extension and network virtualization has led to increased interest of virtualization in industrial automation  ...  In this research, we make use of QoS for CPU, memory and network bandwidth in pursuit of high speed and predictability on a distributed multicore platform which is constructed entirely from open source  ...  We would like to gratefully acknowledge the Software Architecture department/ABB CRC for providing us the necessary equipment, and we would also like to acknowledge VINNOVA, Sweden, for supporting this  ... 
doi:10.1109/etfa.2014.7005062 dblp:conf/etfa/MahmudSV14 fatcat:qjhicxc54rcapi43hdjwcxxl6i

Preesm: A dataflow-based rapid prototyping framework for simplifying multicore DSP programming

Maxime Pelcat, Karol Desnos, Julien Heulot, Clement Guy, Jean-Francois Nezan, Slaheddine Aridhi
2014 2014 6th European Embedded Design in Education and Research Conference (EDERC)  
The current functionalities of this scalable framework cover memory and time analysis, as well as automatic deadlock-free code generation.  ...  Several tutorials are provided with the tool for fast initiation of C programmers to multicore DSP programming.  ...  The framework is open-source and provided with extensive tutorials for easy initiation of C/C++ programmers to multicore DSP programming.  ... 
doi:10.1109/ederc.2014.6924354 fatcat:6lyzuq4v25afti3prgdpfbldey

Memory-based computing for performance and energy improvement in multicore architectures

Kamran Rahmani, Prabhat Mishra, Swarup Bhunia
2012 Proceedings of the great lakes symposium on VLSI - GLSVLSI '12  
In this paper, we propose a novel reconfigurable MBC framework for multicore architectures where each core uses caches for computation using Look Up Tables (LUTs).  ...  Memory-based computing (MBC) is promising for improving performance and energy efficiency in both data-and compute-intensive applications.  ...  As illustrated in Figure 3 , such an extension is achieved for an Portable Instruction Set Architecture (PISA) through identification of the application and modification of the software toolflow to handle  ... 
doi:10.1145/2206781.2206851 dblp:conf/glvlsi/RahmaniMB12 fatcat:4vs5sirdwvhllhpwxvthh5uzhi

Map-Reduce for Machine Learning on Multicore

Cheng-Tao Chu, Sang Kyun Kim, Yi-An Lin, YuanYuan Yu, Gary R. Bradski, Andrew Y. Ng, Kunle Olukotun
2006 Neural Information Processing Systems  
Computers will have increasingly many cores (processors), but there is still no good programming framework for these architectures, and thus no simple and unified way for machine learning to take advantage  ...  We are at the beginning of the multicore era.  ...  Acknowledgments We would like to thank Skip Macy from Intel for sharing his valuable experience in VTune performance analyzer.  ... 
dblp:conf/nips/ChuKLYBNO06 fatcat:d7qws2rljfhrfi467ujrukiyge

De-RISC: Dependable Real-time RISC-V Infrastructure for Safety-critical Space and Avionics Computer Systems

Francisco Gómez-Molinero, Miguel Masmano, Vicente Nicolau, Nils-Johan Wessman, Jan Andersson, Jimmy Le Rhun, Guillem Cabo, Pedro Benedicte, Sergi Alcaide, Jaume Abella
2021 Zenodo  
to commercialize a complete technology stack consisting of an FPGA space grade development board, system-on-chip design and software stack.  ...  The world market for aviation and space computing systems faces a significant shift caused by the loss of momentum of the traditionally used PowerPC and SPARC instruction set architectures in the commercial  ...  space missions for LEON3FT and ARM-Cortex R5 and A9, and is being qualified for multicore platforms [5] ; the Barcelona Supercomputing Center (BSC) as research center for design and analysis of time-predictable  ... 
doi:10.5281/zenodo.5707537 fatcat:rf7keowqlfemfhylg5mtuqad54

StochKit-FF: Efficient Systems Biology on Multicore Architectures [chapter]

Marco Aldinucci, Andrea Bracciali, Pietro Liò, Anil Sorathiya, Massimo Torquati
2011 Lecture Notes in Computer Science  
StochKit-FF is based on the FastFlow programming toolkit for multicores and on the novel concept of selective memory.  ...  We present Stoch-Kit-FF, a parallel version of StochKit, a reference toolkit for stochastic simulations.  ...  Parallel StochKit: StochKit-FF StochKit [1] is an extensible stochastic simulation framework developed in the C++ language.  ... 
doi:10.1007/978-3-642-21878-1_21 fatcat:45jz43xphbhphdhzvtoqbbcqwa

Task Allocation Optimization for Multicore Embedded Systems

Juraj Feljan, Jan Carlson
2014 2014 40th EUROMICRO Conference on Software Engineering and Advanced Applications  
In this paper, we present an optimization mechanism for allocating tasks to cores of a soft real-time embedded system, that aims to minimize end-to-end response times of task chains, while keeping the  ...  In many domains of embedded systems, the increasing performance demands are tackled by increasing performance capacity through the use of multicore technology.  ...  ACKNOWLEDGMENT This work was supported by the Swedish Foundation for Strategic Research via the Ralf 3 project.  ... 
doi:10.1109/seaa.2014.22 dblp:conf/euromicro/FeljanC14 fatcat:fcedujk4wjdjfmyrvibohy7cie

Modeling DVFS and Power-Gating Actuators for Cycle-Accurate NoC-Based Simulators

Davide Zoni, William Fornaciari
2015 ACM Journal on Emerging Technologies in Computing Systems  
This article presents a simulation framework for power-performance analysis of multicore architectures with specific focus on the NoC.  ...  Modeling DVFS and power-gating actuators for cycle-accurate NoC-based simulators.  ...  -Complete, Flexible and Extensible Framework. The proposed framework supports exploration of different multicore design metrics, providing accurate models for the actuators.  ... 
doi:10.1145/2751561 fatcat:4rpwdowomfeirif677l2brlaha

A Survey of Techniques for Reducing Interference in Real-time Applications on Multicore Platforms

Tamara Lugo, Santiago Lozano, Javier Fernandez, Jesus Carretero
2022 IEEE Access  
INDEX TERMS Real-time systems, architecture, multicore, timing analysis, schedulability analysis, WCET, co-runner interference.  ...  This survey reviews the scientific literature on techniques for reducing interference in real-time multicore systems, focusing on the approaches proposed between 2015 and 2020.  ...  [100] presented an extension to the MC2 framework (mixed-criticality on multicore) [116] - [118] .  ... 
doi:10.1109/access.2022.3151891 fatcat:vutgetjua5byxczcivmw2esqtq

A Hierarchical Scheduling Approach for Symmetric Multiprocessing Based Real Time Systems on VxWorks

K. Chakma, S. Debbarma, N. Kar, N. Debbarma, T. Debbarma
2013 Lecture Notes on Software Engineering  
Furthermore, the work can be considered as an extension from the above approaches in the sense that it implements a hierarchical scheduling framework intended for open environments [1] , and Symmetric  ...  An important point here is that a task typically does not finish its execution at the same time always, as execution times and response times vary from one period to another.  ... 
doi:10.7763/lnse.2013.v1.14 fatcat:xq7kpiiejbczpbz3k7cobuh6qm

Multicore Resource Management

Kyle J. Nesbit, Miquel Moreto, Francisco J. Cazorla, Alex Ramirez, Mateo Valero, James E. Smith
2008 IEEE Micro  
An important aspect of multicore chips is improved hardware resource utilization.  ...  However, in multicore chips, processors are concurrently executing threads that compete with each other for fine-grain microarchitecture resources.  ...  Online policies are based primarily on runtime analysis (for example, by using performance counters), while offline policies require an application developer to perform most of the program analysis.  ... 
doi:10.1109/mm.2008.43 fatcat:q7zqg7j4njbyzi6ojn65d3rqta

Multicore Architectures [chapter]

2010 Chapman & Hall/CRC Computational Science  
StochKit-FF is based on the FastFlow programming toolkit for multicores and exploits the novel concept of selective memory.  ...  We present StochKit-FF, a parallel version of StochKit, a reference toolkit for stochastic simulations.  ...  Parallel StochKit: StochKit-FF StochKit [12] is an efficient, extensible stochastic simulation framework developed in the C++ language.  ... 
doi:10.1201/b10442-2 fatcat:kiokswgyrfdnvfjrnpf5gmbbda
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