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Filters
An estimation method of timing mismatch error in hybrid filter bank DACs
2020
IEICE Electronics Express
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This paper presents an estimation method of timing mismatch error in hybrid filter bank digital-to analog converter (HFB DAC). ...
An approximated transfer function of HFB DAC with timing mismatch is derived based on the Taylor series. Then an iteration method is introduced to approach the timing error. ...
Conclusion In this paper, an estimation method of timing mismatch error in HFB DAC is proposed. ...
doi:10.1587/elex.17.20200126
fatcat:54h67qmngvanrfsuqpq5tupbuy
Calibration of static nonlinearity mismatch errors in TIADC based on periodic time-varying adaptive method
2020
IEICE Electronics Express
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The proposed periodic timevarying adaptive calibration method can estimate coefficients of inverse polynomial model directly and capture variations of the nonlinear parameters when environment changes. ...
The nonlinear behaviors of time-interleaved analog-to-digital converter (TIADC) caused by non-ideal circuit implementations degrade performance of TIADC significantly. ...
In [19] , the nonlinear behaviors of TIADC system are modeled with nonlinear hybrid filter bank and it is pointed out nonlinear hybrid filter banks can be used to model offset, gain, time and nonlinear ...
doi:10.1587/elex.17.20200324
fatcat:bjkbi7nnmrcu3fz2kikxkybuy4
Adaptive equalization for calibration of subband hybrid filter banks A/D converters
2009
2009 European Conference on Circuit Theory and Design
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Hybrid Filter Banks (HFB) A/D converters (ADC) are attractive to software-defined radio application, however their high sensitivity to analog imperfections is still a bottleneck for their realization. ...
Thus, the synthesis filter coefficients are iteratively adjusted for compensating the mismatches between the analog part and the digital part. ...
INTRODUCTION In the context of cognitive radio, Hybrid Filter Banks (HFB) A/D converters (ADC) may be an attractive solution to meet the future A/D conversion system requirements [1] . ...
doi:10.1109/ecctd.2009.5275136
dblp:conf/ecctd/SongLPB09
fatcat:smpihxtb3fdbncz2geqwoe5nyi
Recent Advances in High-Resolution Hybrid Discrete-Time Noise-Shaping ADCs
2021
IEEE Open Journal of Solid-State Circuits
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Furthermore, this paper presents a review and addresses the benefits of those hybrid architectures. ...
INDEX TERMS ADC, analog-to-digital converter, DAC, digital-to-analog-converter, hybrid ADC, incremental ADC (I-ADC), delta-sigma modulator, time-Interleaving, extrapolating, noise shaping, successive approximation ...
The modulator oversamples the moving analog input signal, and then the loop filter integrates the residue errors between this input and the estimated output (from the DAC). ...
doi:10.1109/ojsscs.2021.3118668
fatcat:s5mn2rqw2fdghfnms7dphrvvtq
Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters
2018
Journal of Low Power Electronics and Applications
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(DAC) in every cycle. ...
The overview includes discussions of channel offsets and gain mismatches, timing skews, channel bandwidth mismatches, and other considerations for low-power hybrid ADC design. ...
A histogram testing method was employed to evaluate the DNL and INL errors of the hybrid ADC [82] . ...
doi:10.3390/jlpea8020012
fatcat:f2svtsza7zfqfigamblpzpcqfe
A Mismatch Calibration Technique for SAR ADCs Based on Deterministic Self-Calibration and Stochastic Quantization
2020
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
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For medium-to high-resolution applications, the size of the DAC is typically determined by random mismatches. ...
A capacitive DAC is an important building block of a charge-redistribution SAR ADC, for its size has a significant impact on performance. ...
The DNL estimation can be done in the same way as it is done for the DNL measurement of an ADC, e.g. using a histogram-based method in the time domain or using frequency-based methods [8] - [11] . ...
doi:10.1109/tcsi.2020.2985816
fatcat:o57m4mvndzgg5nfs6iiu2l44mi
Multi-channel control for microring weight banks
2016
Optics Express
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We demonstrate 4-channel, 2GHz weighted addition in a silicon microring filter bank. ...
in the presence of inter-channel dependence. ...
Reducing dynamic range mismatch is an important direction for making systemic controller errors negligible compared with dynamic errors, and also reducing the DAC resolution needed to achieve a given accuracy ...
doi:10.1364/oe.24.008895
pmid:27137322
fatcat:5tkpeyd6hbfr7jkvqymqp4f6ry
A 1 GS/s, 31 MHz BW, 76.3 dB dynamic range, 34 mW CT- $$\Updelta\Upsigma$$ Δ Σ ADC with 1.5 cycle quantizer delay and improved STF
2013
Analog Integrated Circuits and Signal Processing
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In this work, an improved STF is achieved by using a combination of feed-forward, feedback and feed-in paths and power consumption is reduced by eliminating the adder opamp. ...
A 1 GS/s Continuous-time Delta-Sigma modulator (CT-∆ΣM) with 31 MHz bandwidth, 76.3 dB dynamic range and 72.5 dB peak-SNDR is reported in a 0.13 µm CMOS technology. ...
The feedback loop can tolerate mismatch errors in the inner DACs (DAC 0 and DAC 3 ) as the errors are noise-shaped by the loop. ...
doi:10.1007/s10470-013-0066-2
fatcat:xceg7cvncvaplbro5unatzm5ui
Tb/s Coherent Optical OFDM Systems Enabled by Optical Frequency Combs
2010
Journal of Lightwave Technology
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It demonstrates an effective way to generate an optical OFDM signal with tens of times wider optical bandwidth than that of analog-to-digital converters and digital-to-analog converters (ADC/DAC). ...
In the first experiment, an optical frequency comb (OFC) generator provides 32 comb lines with less than 5-dB power variation. ...
This demonstrates an effective way to generate an optical signal with tens of times wider bandwidth than that of the ADC/DAC. ...
doi:10.1109/jlt.2010.2053348
fatcat:ue33nfkhk5cexk5siyx62hhxoe
A Digitally Enhanced Dynamically Reconfigurable Analog Platform for Low-Power Signal Processing
2012
IEEE Journal of Solid-State Circuits
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To highlight the potential of this digitally enhanced analog processor, we demonstrate a dynamically reconfigurable image transformer, an arbitrary waveform generator, and a mixed-signal FIR filter. ...
We introduce a new hybrid floating-gate switch matrix, which includes switches that eliminate previously observed mismatch issues to provide highly precise computation. ...
This programming method uses one FG as both the programmed device and the in-circuit device, so the mismatch between the program-time and run-time devices for a particular SM address has been eliminated ...
doi:10.1109/jssc.2012.2194847
fatcat:i7vwdjj6z5fdjmcbrcerlfnak4
A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS
2018
IEEE Journal of Solid-State Circuits
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A 5.0-mW TX is achieved when delivering an output power of 0 dBm with a frequency-shift keying error of only 1.89%. ...
By maximally reducing the required radio frequency and analog front-end components in RX, an RX power consumption of 2.3 mW is achieved with a −94 dBm sensitivity. ...
(TX) with an FSK error of 1.89% at an output of 0 dBm in a 65-nm CMOS process. ...
doi:10.1109/jssc.2018.2878822
fatcat:a57tux2xdvfqzghy7enihhneeq
2019 Index IEEE Transactions on Circuits and Systems I: Regular Papers Vol. 66
2019
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
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Asynchronous Finite-Time Filtering of Networked Switched Systems and its Application: an Event-Driven Method. ...
., +, TCSI Oct. 2019
3896-3905
Discrete time filters
An On-Chip Built-in Linearity Estimation Methodology and Hardware
Implementation. ...
Analysis of SRAM Enhancements Through Sense Amplifier ...
doi:10.1109/tcsi.2020.2966967
fatcat:f663jj5g45e3peggn3gwn5jys4
Regularized minimum variance distortionless response-based cepstral features for robust continuous speech recognition
2015
Speech Communication
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In multi-condition training, the RMCC, RRMCC, and NRMCC perform slightly better in terms of the average word error rate than the rest of the front-ends used in this work. ...
In clean training conditions, on average, the RRMCC and NRMCC provide significant reductions in word error rate over the rest of the front-ends. ...
Acknowledgement The authors would like to thank the reviewers for their relevant and constructive remarks, which have enabled us to significantly improve the quality of the paper. ...
doi:10.1016/j.specom.2015.07.007
fatcat:2i4niheg5rcrbfaybtcbqyog6u
A Frequency-Translating Hybrid Architecture for Wide-Band Analog-to-Digital Converters
2007
IEEE transactions on circuits and systems - 2, Analog and digital signal processing
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A proof of concept board-level implementation of the FTH-ADC is used to analyze the effects of major analog non-idealities and errors. Error measurement and compensation methods are presented. ...
200 MHz is implemented with an effective number of bits of at least 7 bits over the entire 100 MHz input bandwidth. iii In addition, one path of an 8-GHz, 4-bit, FTH-ADC system, including a highly-linear ...
The hybrid architecture is similar to that of the QMF-FBD except for the analysis filter bank, which is an array of continuous-time filters instead of discrete-time analog filters. ...
doi:10.1109/tcsii.2007.893734
fatcat:sccrqdqpcjgsroyeelwtvpbpny
2018 IndexIEEE Transactions on Very Large Scale Integration (VLSI) SystemsVol. 26
2018
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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., see 2723-2736
, VLSI Design of an ML-Based Power-Efficient Motion Estimation Controller for Intelligent Mobile Systems; TVLSI Feb. 2018 262-271 Hsieh, Y., see Tsai, Y., TVLSI May 2018 945-957 ...
Yang, J., +, TVLSI Dec. 2018 2628-2640
Fast Analysis of Time Interval Error in Current-Mode Drivers. ...
., +, TVLSI Aug. 2018 1580-1584
Circuit noise
Fast Analysis of Time Interval Error in Current-Mode Drivers. ...
doi:10.1109/tvlsi.2019.2892312
fatcat:rxiz5duc6jhdzjo4ybcxdajtbq
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