765 Hits in 5.7 sec

Session 13 Overview: Non-Volatile Memories: Memory Subcommittee

2020 2020 IEEE International Solid- State Circuits Conference - (ISSCC)  
DRAM and flash memories.  ...  The 4b/cell of 3D NAND flash technology becomes practical in many applications and the high-speed SLC NAND flash has great potential to improve computing system performance by filling the latency gap between  ...  DRAM and flash memories.  ... 
doi:10.1109/isscc19947.2020.9062981 fatcat:cudhpjoj75bgdbxmijebgesc2e

Introduction to Advanced Semiconductor Memories [chapter]

2009 Advanced Semiconductor Memories  
An overview of Intel's 3-V StrataFlash NOR-based memory, a proposed multilevel 64-Mb NAND flash memory design, a 512-Mb NAND flash memory from Toshiba Corp., and a 256-Mb multilevel cell AND flash memory  ...  Memory technology for embedded memory has a wide variation, ranging from small blocks of ROMs, hundreds of kilobytes for the cache RAMs, high density (several megabits) of DRAMs, and small to medium density  ... 
doi:10.1109/9780470544136.ch1 fatcat:5agoaobfx5aqfmmsnmsj4a4mwy

Technology scaling impact on NOR and NAND flash memories and their applications

Harry Pon
2006 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings  
The addition of NAND Flash into the PC memory hierarchy delivers better performance, improved power savings and a richer user experience.  ...  Despite the challenges imposed by memory technology scaling, flash memory solutions will evolve to an ever changing variety of application needs with lower power, ever diversified and more efficient solutions  ...  Acknowledgments System Architects, Flash Design and Development Engineering colleagues O.Jungroth; G.Gould; K.Rao, P.Chen, M.Leinwander, R. Coulsen, K.Grimsrud, for sharing their expertise and data.  ... 
doi:10.1109/icsict.2006.306440 fatcat:g7426yawurglvc4k66af4lnkoq

Application specific non-volatile primary memory for embedded systems

Kwangyoon Lee, Alex Orailoglu
2008 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis - CODES/ISSS '08  
However, in NAND flash memory, the intrinsic costs for the read and write accesses are highly disproportionate in performance and access granularity.  ...  The consequent data management complexity and performance deterioration have precluded the adoption of NAND flash memory.  ...  In [3] , OneNAND TM , a hybrid NAND flash memory, has been introduced as a high-performance non-volatile memory for embedded systems.  ... 
doi:10.1145/1450135.1450144 dblp:conf/codes/LeeO08 fatcat:26onssjnvzaubmhjsxvn6m3oai

Fast, Energy Efficient Scan inside Flash Memory

Sungchan Kim, Hyunok Oh, Chanik Park, Sangyeun Cho, Sang-Won Lee
2011 Very Large Data Bases Conference  
While data from flash memory are transferred, a target database operation is applied to the data stream on the fly without any delay.  ...  As a result, the system I/O bus remains a bottleneck, and the abundant flash memory bandwidth as well as the computing capabilities inside SSD is largely untapped.  ...  The FMC can be implemented as dedicated hardware for high performance and power efficiency or an application-specific instruction-set processor to support diverse NAND flash memory commands.  ... 
dblp:conf/vldb/KimOPCL11 fatcat:p7mrtq4qfbgklkbicrv2osjsqm

Advances in Emerging Memory Technologies: From Data Storage to Artificial Intelligence

Gabriel Molas, Etienne Nowak
2021 Applied Sciences  
It begins with the presentation of stand-alone and embedded memory technology evolution, since the appearance of Flash memory in the 1980s.  ...  This paper presents an overview of emerging memory technologies.  ...  Thus, there is space for a new memory to enter the hierarchy, fill this gap between DRAM and NAND, and improve computing system performance [33] .  ... 
doi:10.3390/app112311254 fatcat:pg4iqzg4yfc2vb2lh2mgkyqafq

Modeling, Architecture, and Applications for Emerging Memory Technologies

Yuan Xie
2011 IEEE Design & Test of Computers  
Traditional memory hierarchy design consists of embedded memory (such as SRAM and embedded DRAM [eDRAM]) for on-chip caches, commodity DRAM for main memory, and magnetic hard disk drives (HDDs) for storage  ...  Such emerging nonvolatile memory (NVM) technologies combine the speed of SRAM, the density of DRAM, and the nonvolatility of flash memory, and so become very attractive as alternatives for the future memory  ...  Traditional memory hierarchy design consists of embedded memory (such as SRAM and embedded DRAM [eDRAM]) for on-chip caches, commodity DRAM for main memory, and magnetic hard disk drives (HDDs) for storage  ... 
doi:10.1109/mdt.2011.20 fatcat:rmgrdwnxd5hpnla4whhmanomt4

Rethinking memory system design for data-intensive computing

Onur Mutlu
2015 2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)  
 Low-cost system-level tolerance of memory errors   Cai+, "Error Analysis and Retention-Aware Error Management for NAND Flash Memory," Intel Technology Journal 2013.  ...   Cai+, "Neighbor-Cell Assisted Error Correction for MLC NAND Flash Memories," SIGMETRICS 2014.  ... 
doi:10.1109/samos.2015.7363650 dblp:conf/samos/Mutlu15 fatcat:fc5a6u4sinhotaibqt6bsull2a


Taeho Kgil, Trevor Mudge
2006 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems - CASES '06  
We propose an architecture that uses NAND flash memory to reduce main memory power in web server platforms.  ...  This is a result of using flash memory, which consumes orders of magnitude less idle power than DRAM and is twice as dense.  ...  In [22] , it was shown that flash memory could be used directly for high performance code execution by adding an SRAM.  ... 
doi:10.1145/1176760.1176774 dblp:conf/cases/KgilM06 fatcat:tbfiqjsmi5f5dg64afz3tqprxa

Welcome and Opening Remarks

William D. Rhine, Lars Bode
2018 Breastfeeding Medicine  
node (CMOS5) 0.56[mu]m[superscript 2] SRAM cell design for very low operation voltage A 0.18[mu]m logic-based MRAM technology for high performance nonvolatile memory applications Fabrication of HfSiON  ...  metal electrode Design and proof of high quality HfAlO[subscript x] film formation for MOSCAPs and nMOSFETs through layer-by-layer deposition and annealing process Novel multi-bit SONOS type flash memory  ...  cell size down to 8F[superscript 2] for high density embedded nonvolatile memory applications New buried bit-line NAND (BiNAND) flash memory for data storage (110)-surface strained-SOI CMOS devices with  ... 
doi:10.1089/bfm.2018.29069.wdr pmid:29624418 fatcat:vw44nj7nwfex7nkdssnc55xk2a

Phase Change and Magnetic Memories for Solid-State Drive Applications

Cristian Zambelli, Gabriele Navarro, Veronique Sousa, Ioan Lucian Prejbeanu, Luca Perniola
2017 Proceedings of the IEEE  
The state-of-the-art Solid State Drives now heterogeneously integrate NAND Flash and DRAM memories to partially hide the limitation of the non-volatile memory technology.  ...  However, due to the increased request for storage density coupled with performance that positions the storage tier closer to the latency of the processing elements, NAND Flash are becoming a serious bottleneck  ...  To this extent, sophisticated memory controllers need to be embedded in the drive to hide the weaknesses of NAND Flash by reducing their failure rate especially for multi-level technologies.  ... 
doi:10.1109/jproc.2017.2710217 fatcat:fof3pr2ixjfqdd3f226s4qqh7e

Overview of emerging nonvolatile memory technologies

Jagan Meena, Simon Sze, Umesh Chand, Tseung-Yuen Tseng
2014 Nanoscale Research Letters  
Therefore, this review is devoted to the rapidly developing new class of memory technologies and scaling of scientific procedures based on an investigation of recent progress in advanced Flash memory devices  ...  A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly  ...  Acknowledgements First of all, the authors would like to thank and gratefully acknowledge all corresponding publishers for the kind permission to reproduce their figures and related description, used in  ... 
doi:10.1186/1556-276x-9-526 pmid:25278820 pmcid:PMC4182445 fatcat:dhetgjf6qfhidhb5nmya3vj6na

WPA: Write Pattern Aware Hybrid Disk Buffer Management for Improving Lifespan of NAND Flash Memory

Jun-Hyeong Choi, Kyung Min Kim, Jong Wook Kwak
2020 IEEE transactions on consumer electronics  
Therefore, researchers have investigated ways for improving the lifespan of flash memories.  ...  NAND flash memories are suitable as portable consumer device storages, as they have several advantages such as non-volatility, high density and low power consumption.  ...  positive effect for the system performance in terms of access latency, power consumption and lifespan of NAND flash memories.  ... 
doi:10.1109/tce.2020.2981618 fatcat:a7wj2456avhcdf2plk5njqzu3q

PTL: PCM Translation Layer

Zili Shao, Naehyuck Chang, Nikil Dutt
2012 2012 IEEE Computer Society Annual Symposium on VLSI  
PCM (Phase Change Memory) has been used as NOR flash replacement in embedded systems , and poses interesting system-level challenges for transparent exploitation of these memory structures by embedded  ...  We study the requirements for transparently managing PCM in embedded systems, and propose the system architecture of PTL.  ...  Table I A I COMPARISON OF PCM WITH DRAM AND NAND FLASH MEMORY [17] .  ... 
doi:10.1109/isvlsi.2012.75 dblp:conf/isvlsi/ShaoCD12 fatcat:r55vuasxf5byfmvxj3j7akazqq

The Apparatus and Enabling of a Code Balanced System

Tony Benavides, Justin Treon, Weide Chang
2007 Fourth International Conference on Information Technology (ITNG'07)  
Success in the embedded world revolves around two key concepts: cost effectiveness and performance.  ...  This type of memory sub-system defines the execution of code and data directly from NOR flash memory. An additional memory architecture of choice is called a Store and Download architecture.  ...  Related Research An XIP memory model consists of a system that has NOR flash and PSRAM/DRAM within it. The code is executed from the NOR flash memory.  ... 
doi:10.1109/itng.2007.191 dblp:conf/itng/BenavidesTC07 fatcat:knkozlxjtbhfdbvzlvae6ujysy
« Previous Showing results 1 — 15 out of 765 results