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Algorithm Transformation for FPGA Implementation

Donald G. Bailey, Christopher T. Johnston
<span title="">2010</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/4s2ejwsygze4vfu5lsndw5m4ny" style="color: black;">2010 Fifth IEEE International Symposium on Electronic Design, Test &amp; Applications</a> </i> &nbsp;
To obtain an efficient hardware architecture, one that makes use of the available parallelism, the algorithms need to be transformed. Eleven such transformations are identified and explained.  ...  These languages are often used to accelerate legacy software algorithms by porting them to an FPGA based hardware implementation.  ...  ALGORITHM TRANSFORMATION PROCESS The key to an efficient hardware implementation is not to port an existing serial algorithm, but to transform the algorithm. This is a three step process.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/delta.2010.17">doi:10.1109/delta.2010.17</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/delta/BaileyJ10.html">dblp:conf/delta/BaileyJ10</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/bpvlrwvzrbckfcihm4o3co2wmi">fatcat:bpvlrwvzrbckfcihm4o3co2wmi</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20200127034137/http://sprg.massey.ac.nz/pdfs/2010_DELTA_77.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/b1/c5/b1c5268909ffba6730742f438d7ae7ea0c58d165.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/delta.2010.17"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Front Matter [chapter]

<span title="2011-06-02">2011</span> <i title="John Wiley &amp; Sons (Asia) Pte Ltd"> Design for Embedded Image Processing on FPGAs </i> &nbsp;
Implementing an image processing algorithm (or indeed any algorithm) on an FPGA, therefore, consists of determining the underlying architecture of an algorithm, mapping that architecture onto the resources  ...  This book addresses this issue by providing not only algorithms for image processing operations, but also underlying architectures that can be used to implement them efficiently.  ...  ways of implementing image processing algorithms.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1002/9780470828519.fmatter">doi:10.1002/9780470828519.fmatter</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/7ybavqcdu5bz5byhjtm7wbn4py">fatcat:7ybavqcdu5bz5byhjtm7wbn4py</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20191129002058/https://onlinelibrary.wiley.com/doi/pdfdirect/10.1002/9780470828519.fmatter" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/f7/55/f75501337a7650825237a84b6555c3e7537369b1.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1002/9780470828519.fmatter"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> wiley.com </button> </a>

Design and Implementation of True Parallelism Quad-Engine Cybersecurity Architecture on FPGA

Nada Qaim Mohammed, Amiza Amir, Muataz Hammed Salih, Badlishah Ahmad
<span title="">2022</span> <i title="The Science and Information Organization"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/2yzw5hsmlfa6bkafwsibbudu64" style="color: black;">International Journal of Advanced Computer Science and Applications</a> </i> &nbsp;
All data processed in engines is encrypted via AES algorithm that implemented as a significant part of engine architecture.  ...  The obtained results increased the throughput by four times, with 153,600Mbps, that make this computing architecture efficient and suitable for fast applications such as IoT and cybersecurity level of  ...  These results make this introduced architecture efficient and suitable for fast image processing, such as using complex cyber security algorithms for secure information. Fig. 1 . 1 Fig. 1.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.14569/ijacsa.2022.0130183">doi:10.14569/ijacsa.2022.0130183</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/mykmy66x2zearh2kwdosw3myye">fatcat:mykmy66x2zearh2kwdosw3myye</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20220208041300/https://thesai.org/Downloads/Volume13No1/Paper_83-Design_and_Implementation_of_True_Parallelism.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/00/77/007774e1228cc7550f3298d912465c4eeb1e77cf.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.14569/ijacsa.2022.0130183"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="unlock alternate icon" style="background-color: #fb971f;"></i> Publisher / doi.org </button> </a>

Special issue on design and architectures of real-time image processing in embedded systems

Daniel Chillet, Michael Hübner
<span title="2014-02-04">2014</span> <i title="Springer Nature"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/ihxuyfsqpjeoxn5hsmj4p7gmpy" style="color: black;">Journal of Real-Time Image Processing</a> </i> &nbsp;
Image processing for medicine, automotive, and for video compression is the main algorithm that has been addressed by the authors of the Design and Architecture for Image and Signal Processing (DASIP)  ...  Image processing is one of the major applications in embedded domain, which requires high effort in computation.  ...  Image processing for medicine, automotive, and for video compression is the main algorithm that has been addressed by the authors of the Design and Architecture for Image and Signal Processing (DASIP)  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/s11554-014-0401-6">doi:10.1007/s11554-014-0401-6</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/f2mhcmcttbel5fpdfziqwgkqqq">fatcat:f2mhcmcttbel5fpdfziqwgkqqq</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20180726100947/https://link.springer.com/content/pdf/10.1007%2Fs11554-014-0401-6.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/a3/35/a33531e9be1f3699e746bc8b0b297f1cc909a05b.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/s11554-014-0401-6"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> springer.com </button> </a>

iDocChip: A Configurable Hardware Architecture for Historical Document Image Processing

Menbere Kina Tekleyohannes, Vladimir Rybalkin, Muhammad Mohsin Ghaffar, Javier Alejandro Varela, Norbert Wehn, Andreas Dengel
<span title="2021-01-30">2021</span> <i title="Springer Science and Business Media LLC"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/6ni4hdyv7zdtzjxnzscp53l5ry" style="color: black;">International journal of parallel programming</a> </i> &nbsp;
In this paper, we focus on one of the most crucial processing steps in the anyOCR system: Text and Image Segmentation, which makes use of a multi-resolution morphology-based algorithm.  ...  Moreover, an optimized $$\hbox {FPGA}$$ FPGA -based hybrid architecture of this anyOCR step along with its optimized software implementations are presented.  ...  design an efficient hardware architecture, with a negligible loss of accuracy.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/s10766-020-00690-y">doi:10.1007/s10766-020-00690-y</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/mhfyemm23zg7vix7pyglej4wgu">fatcat:mhfyemm23zg7vix7pyglej4wgu</a> </span>
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VHDL based Hardware Architecture of a High Performance Image Edge Detection Algorithm

Hanene Rouabeh, Chokri Abdelmoula, Mohamed Masmoudi
<span title="2014-04-18">2014</span> <i title="Foundation of Computer Science"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/b637noqf3vhmhjevdfk3h5pdsu" style="color: black;">International Journal of Computer Applications</a> </i> &nbsp;
This article presents the software and hardware implementation of a low cost and high performance image edge detection algorithm.  ...  The software implementation of the developed algorithm using MATLAB tool is discussed in this paper, as well as the hardware architecture developed using VHDL language.  ...  To check the validity and efficiency of the hardware architecture, an RTL simulation was done using ModelSim Altera. For the simulation a 258x195 image is used and shown in Figure 10 (a).  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.5120/15935-5208">doi:10.5120/15935-5208</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/6e3su5yytnbtfnljk5jwo24cya">fatcat:6e3su5yytnbtfnljk5jwo24cya</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20180604085936/https://research.ijcaonline.org/volume91/number12/pxc3895208.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/1c/6f/1c6fc6a9e1a8804756abfabc6ff3be303eb92537.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.5120/15935-5208"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> Publisher / doi.org </button> </a>

Onboard Processing of Synthetic Aperture Radar Backprojection Algorithm in FPGA

David Mota, Helena Cruz, Pedro R. Miranda, Rui Policarpo Duarte, Jose T. de Sousa, Horacio C. Neto, Mario P. Vestias
<span title="">2022</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/b2n2tpw5ang73osulebz6bm4ju" style="color: black;">IEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing</a> </i> &nbsp;
This article proposes a configurable hardware core for the execution of the backprojection algorithm with high performance and energy efficiency.  ...  Radar data streams are acquired by an aircraft or satellite and sent to a ground station to be processed in order to extract images from the data since these processing algorithms are computationally demanding  ...  SAR imaging is a remote sensing technology that can benefit of onboard processing. This article proposes an FPGA-based hardware core for onboard processing of SAR images.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/jstars.2022.3169828">doi:10.1109/jstars.2022.3169828</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/uwnv7putlnfmpflkao4gkfoffe">fatcat:uwnv7putlnfmpflkao4gkfoffe</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20220520191839/https://ieeexplore.ieee.org/ielx7/4609443/9656571/09762545.pdf?tp=&amp;arnumber=9762545&amp;isnumber=9656571&amp;ref=" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/e5/ac/e5ac30add293850a248cc7578802bb72cca0da5f.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/jstars.2022.3169828"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="unlock alternate icon" style="background-color: #fb971f;"></i> ieee.com </button> </a>

Design and Architectures for Signal and Image Processing

Markus Rupp, Ahmet T. Erdogan, Bertrand Granado
<span title="">2009</span> <i title="Springer Nature"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/qdjkc7427rgarmzaexozmec3eq" style="color: black;">EURASIP Journal on Embedded Systems</a> </i> &nbsp;
This Special Issue of the EURASIP Journal of embedded systems is intended to present innovative methods, tools, design methodologies, and frameworks for algorithm-architecture matching approach in the  ...  design flow including system level design and hardware/software codesign, RTOS, system modeling and rapid prototyping, system synthesis, design verification, and performance analysis and estimation.  ...  The system relies on the utilization of image processing algorithms in order to increase the trigger efficiency.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1155/2009/674308">doi:10.1155/2009/674308</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/l2npgnxwavb3xgmedjdzwklv6y">fatcat:l2npgnxwavb3xgmedjdzwklv6y</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170811082033/https://jes-eurasipjournals.springeropen.com/track/pdf/10.1155/2009/674308?site=jes.eurasipjournals.springeropen.com" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/79/15/7915a96005ec7de705360051972c33c9078c3e1a.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1155/2009/674308"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="unlock alternate icon" style="background-color: #fb971f;"></i> hindawi.com </button> </a>

Design space exploration for image processing architectures on FPGA targets [article]

Chandrajit Pal, Avik Kotal, Asit Samanta, Amlan Chakrabarti, Ranjan Ghosh
<span title="2014-04-15">2014</span> <i > arXiv </i> &nbsp; <span class="release-stage" >pre-print</span>
those one can get just merely porting the image processing software algorithms to hardware.  ...  In this paper, we intend to present an elaborate review, based on our expertise and experiences, on undertaking necessary transformation to an image processing software algorithm including the optimization  ...  of Calcutta for the experimental equipments.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener" href="https://arxiv.org/abs/1404.3877v1">arXiv:1404.3877v1</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/2qwmaxclxfh35admgz5tnk6fiy">fatcat:2qwmaxclxfh35admgz5tnk6fiy</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20201001060234/https://arxiv.org/ftp/arxiv/papers/1404/1404.3877.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/69/5c/695cd1990a775ca741e04af92889093447562fe0.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener" href="https://arxiv.org/abs/1404.3877v1" title="arxiv.org access"> <button class="ui compact blue labeled icon button serp-button"> <i class="file alternate outline icon"></i> arxiv.org </button> </a>

Automated Design of an ASIP for Image Processing Applications [chapter]

Henjo Schot, Henk Corporaal
<span title="">2000</span> <i title="Springer Berlin Heidelberg"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/2w3awgokqne6te4nvlofavy5a4" style="color: black;">Lecture Notes in Computer Science</a> </i> &nbsp;
A hardware feasible architecture is presented that efficiently executes a set of image processing algorithms and performs almost equally or better than alternative, commercial-available solutions do.  ...  This paper presents the design of highly optimized TTA architectures for image processing applications. An automatic processor design framework as described in [2] is used.  ...  Introduction In this paper, we show the design of an application specific instruction set processor (ASIP) for a set of image processing algorithms.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/3-540-44520-x_156">doi:10.1007/3-540-44520-x_156</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/atjwgen4gzeexhgkiwyqz7rmci">fatcat:atjwgen4gzeexhgkiwyqz7rmci</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20081002142633/http://ce.et.tudelft.nl/publicationfiles/300_175_19001105.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/d8/4d/d84d7915f8f14b0035c441d8b5da96df21aa6762.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/3-540-44520-x_156"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> springer.com </button> </a>

Hardware efficient architecture for compressed imaging

Jun Luo, Qijun Huang, Sheng Chang, Hao Wang
<span title="">2014</span> <i title="Institute of Electronics, Information and Communications Engineers (IEICE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/fvf4s3u4inbjpnfv6imirwcvam" style="color: black;">IEICE Electronics Express</a> </i> &nbsp;
Experiment results show that the proposed hardware architecture can efficiently reduce the process time in encoding and decoding of a 512 # 512 image.  ...  This paper presents efficient hardware architecture based on adaptive sampling and separable reconstructing.  ...  No hardware architecture of SLR algorithm for CS has been reported to the best of my knowledge. The real-time processing can be achieved for solving a 512 Â 512 image.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1587/elex.11.20140562">doi:10.1587/elex.11.20140562</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/k6ek6655xnhonclatwck5uo63y">fatcat:k6ek6655xnhonclatwck5uo63y</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20181102030610/https://www.jstage.jst.go.jp/article/elex/11/14/11_11.20140562/_pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/21/a3/21a399fbf36de71d5cce20b719f39a27f7e41b9d.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1587/elex.11.20140562"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> Publisher / doi.org </button> </a>

Special issue: Design and architectures for real-time signal and image processing

Michael Huebner
<span title="2018-05-25">2018</span> <i title="Springer Nature"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/ihxuyfsqpjeoxn5hsmj4p7gmpy" style="color: black;">Journal of Real-Time Image Processing</a> </i> &nbsp;
The hardware architecture-oriented contributions show specialized hardware blocks for an improved data throughput.  ...  The Conference on Design and Architectures for Signal and Image Processing-DASIP addresses the development of complex applications involving signal, image and control processing based on a new approach  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/s11554-018-0790-z">doi:10.1007/s11554-018-0790-z</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/gqjhxob3gnghdkrv46jaq6itg4">fatcat:gqjhxob3gnghdkrv46jaq6itg4</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20190505080604/https://link.springer.com/content/pdf/10.1007%2Fs11554-018-0790-z.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/01/c0/01c011374a416e8406832cc1ce7ad982ca94d69f.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/s11554-018-0790-z"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> springer.com </button> </a>

Power efficient dataflow design for a heterogeneous smart camera architecture

Deepayan Bhowmik, Paulo Garcia, Andrew Wallace, Robert Stewart, Greg Michaelson
<span title="">2017</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/nq3a3wrr3ja27nres7uhrlmdfi" style="color: black;">2017 Conference on Design and Architectures for Signal and Image Processing (DASIP)</a> </i> &nbsp;
The proposed design flow encompasses image processing algorithm implementation, hardware & software integration and network connectivity through a unified model.  ...  Smart camera architectures are an emerging technology and a foundation of security and safety frameworks in modern vision systems.  ...  ACKNOWLEDGEMENTS We acknowledge the support of the Engineering and Physical Sciences Research Council, GR EP K/009931/1 and a HEIF Impact fellowship at Sheffield Hallam University.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/dasip.2017.8122128">doi:10.1109/dasip.2017.8122128</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/dasip/BhowmikGWSM17.html">dblp:conf/dasip/BhowmikGWSM17</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/evlha7r6jff4ngwfl6mp3kbmfu">fatcat:evlha7r6jff4ngwfl6mp3kbmfu</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20190810033748/http://shura.shu.ac.uk/16301/1/SCA_FPGA.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/9c/44/9c44ecb293ae8beb0c79760b3c71ac6864a5a836.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/dasip.2017.8122128"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Resource Efficient Hardware Architecture for Fast Computation of Running Max/Min Filters

Cesar Torres-Huitzil
<span title="">2013</span> <i title="Hindawi Limited"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/nxzqpsogkbe55mjq33syzghf2e" style="color: black;">The Scientific World Journal</a> </i> &nbsp;
This paper presents a hardware architecture for real-time computation of running max/min filters based on the van Herk/Gil-Werman (HGW) algorithm.  ...  The applicability of the architecture is shown for local adaptive image thresholding.  ...  Conclusions An efficient implementation of a fast algorithm for arbitrary length max/min filters has been presented.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1155/2013/108103">doi:10.1155/2013/108103</a> <a target="_blank" rel="external noopener" href="https://www.ncbi.nlm.nih.gov/pubmed/24288456">pmid:24288456</a> <a target="_blank" rel="external noopener" href="https://pubmed.ncbi.nlm.nih.gov/PMC3833061/">pmcid:PMC3833061</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/gnztxwayzrbylk6mps75ae5ksa">fatcat:gnztxwayzrbylk6mps75ae5ksa</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20190503010409/http://downloads.hindawi.com/journals/tswj/2013/108103.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/cb/be/cbbefb1e050fdf125c5479fec96793475661ccc4.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1155/2013/108103"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="unlock alternate icon" style="background-color: #fb971f;"></i> hindawi.com </button> </a> <a target="_blank" rel="external noopener" href="https://www.ncbi.nlm.nih.gov/pmc/articles/PMC3833061" title="pubmed link"> <button class="ui compact blue labeled icon button serp-button"> <i class="file alternate outline icon"></i> pubmed.gov </button> </a>

FPGA based accelerator for visual features detection

Francois Brenot, Philippe Fillatreau, Jonathan Piat
<span title="">2015</span> <i title="IEEE"> 2015 IEEE International Workshop of Electronics, Control, Measurement, Signals and their Application to Mechatronics (ECMSM) </i> &nbsp;
Design of an hardware architecture for NMS The output score image is composed by regions which correspond to each corner found.  ...  In section III-B, we describe our approach for the design of an original hardware architecture allowing to efficiently integrate a non maxima suppression functionality on FPGA ; the processing can be configured  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/ecmsm.2015.7208697">doi:10.1109/ecmsm.2015.7208697</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/hekgnsdkgbh57gmdjwbwlapzzm">fatcat:hekgnsdkgbh57gmdjwbwlapzzm</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20190430211245/https://hal.archives-ouvertes.fr/hal-01300912/file/ECMSM2015.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/e6/0b/e60bdfd8edf4b779aae67048acc5ef07e1615414.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/ecmsm.2015.7208697"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>
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