Filters








88,151 Hits in 9.0 sec

High-Level Crosstalk Defect Simulation Methodology for System-on-Chip Interconnects

X. Bai, S. Dey
<span title="">2004</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/rl7xk4fwazdrred2difr6v3lii" style="color: black;">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems</a> </i> &nbsp;
In this paper, we present an efficient high-level crosstalk-defect simulation methodology for interconnects dominated by capacitive coupling effects.  ...  For system-on-chips (SoC) using nanometer technologies, buses and long interconnects are susceptible to crosstalk defects that may lead to functional and timing failures.  ...  On-chip interconnect is becoming a critical determinant for the performance and reliability of high-frequency low-power system-on-chip (SoC) designs.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tcad.2004.833612">doi:10.1109/tcad.2004.833612</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/yknb37myrze6hira6sihsksr3i">fatcat:yknb37myrze6hira6sihsksr3i</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20060906020851/http://esdat.ucsd.edu/~xibai/esdat/publication/TCAD_Sept_04.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/c0/7e/c07ef44e965a0ed0abe7065f3e0fac9776e14d84.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tcad.2004.833612"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Quasi-Resonant Interconnects: A Low Power, Low Latency Design Methodology

Jonathan Rosenfeld, Eby G. Friedman
<span title="">2009</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/uqbr2omxsbdgtaxslmblka2nnu" style="color: black;">IEEE Transactions on Very Large Scale Integration (vlsi) Systems</a> </i> &nbsp;
The methodology focuses on developing an accurate analytic distributed model of the on-chip interconnect and inductor to obtain both low power and low latency.  ...  Design and analysis guidelines for quasi-resonant interconnect networks (QRN) are presented in this paper.  ...  They would also like to acknowledge one of the reviewers in particular for his discussion regarding Pupin coils. The reviewers' suggestions enabled the authors to significantly improve this paper.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tvlsi.2008.2011197">doi:10.1109/tvlsi.2008.2011197</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/rj6ioahjabe5bnwoduvoekzweu">fatcat:rj6ioahjabe5bnwoduvoekzweu</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20090709145007/http://www.ece.rochester.edu/users/friedman/papers/TVLSI_09_Quasi.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/0e/31/0e314f4bfd3cce557a7dd40cea34c757b4288b22.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tvlsi.2008.2011197"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Editorial

Davide Bertozzi, Giorgos Dimitrakopoulos, Sören Sonntag
<span title="2014-04-26">2014</span> <i title="Springer Nature"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/uu3klqqxhvao7lljdlxvdqib6e" style="color: black;">Design automation for embedded systems</a> </i> &nbsp;
That might be an on-chip interconnect for modern embedded systems or an off-chip interconnect for powerful HPC solutions.  ...  At the same time, evolution is constrained by a design complexity crisis and by power consumption limitations, where performance gains cannot rely on technology scaling.  ...  -Automated Design Space Exploration for FPGA-based Heterogeneous Interconnects presents an automated NoC synthesis methodology targeting FPGA technologies.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/s10617-014-9136-7">doi:10.1007/s10617-014-9136-7</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/qmjth3zpmjefrgdxaactfvcyje">fatcat:qmjth3zpmjefrgdxaactfvcyje</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20180728090738/https://link.springer.com/content/pdf/10.1007%2Fs10617-014-9136-7.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/50/a2/50a281b7a9bc37ddb2d0a79edadf75c6e603d3c1.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/s10617-014-9136-7"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> springer.com </button> </a>

A design methodology for application-specific networks-on-chip

Jiang Xu, Wayne Wolf, Joerg Henkel, Srimat Chakradhar
<span title="2006-05-01">2006</span> <i title="Association for Computing Machinery (ACM)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/3yu4mbaainhw5gol4yayc35pfe" style="color: black;">ACM Transactions on Embedded Computing Systems</a> </i> &nbsp;
statistical communication traces for cycle-accurate performance analysis, (4) is based on standardized network component library and floorplan to estimate power and area, (5) adapts an industrial-grade  ...  The growing complexity of SoC designs makes on-chip communication subsystem design as important as computation subsystem design.  ...  Ho and Pinkston [2003] presented a NoC design methodology based on wellbehaved communications. Xu et al. [2005] proposed a general design, modeling, and analysis methodology for any type of NoC.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1151074.1151076">doi:10.1145/1151074.1151076</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/6xduw4pvwfh6zncpgqsjwxc5l4">fatcat:6xduw4pvwfh6zncpgqsjwxc5l4</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170921233219/http://www.ee.ust.hk/~eexu/publications/J_TECS2006.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/17/16/17161b537d13880a7c075d39908235b42c5305ab.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1151074.1151076"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

Impact of small process geometries on microarchitectures in systems on a chip

D. Sylvester, K. Keutzer
<span title="">2001</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/yfvtieuumfamvmjlc255uckdlm" style="color: black;">Proceedings of the IEEE</a> </i> &nbsp;
Having determined this, we then reconsider the impact of future processes on integrated-circuit design methodology.  ...  We then proceed to quantify the precise impact of interconnect, including dynamic delay due to noise, on the performance of high-end integrated circuit designs.  ...  Shilman for information on packet-switched networks.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/5.920579">doi:10.1109/5.920579</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/xvpfrpy5rzgcnbancnnqenl27y">fatcat:xvpfrpy5rzgcnbancnnqenl27y</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20060915003349/http://users.ece.gatech.edu/~limsk/www/pdfs/00920579.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/86/8a/868a0b3079c0f855e9e63e1599c081e390b8a78f.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/5.920579"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Machine Learning Based Energy-Efficient Design Approach for Interconnects in Circuits and Systems

Hung Khac Le, SoYoung Kim
<span title="2021-01-20">2021</span> <i title="MDPI AG"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/smrngspzhzce7dy6ofycrfxbim" style="color: black;">Applied Sciences</a> </i> &nbsp;
In this paper, we propose an efficient design methodology for energy-efficient off-chip interconnect.  ...  Additionally, a specified objective function to select low-loss and low-noise structure is employed to determine the optimal case from a large design space.  ...  Conclusions This paper proposes an energy-efficient design methodology for low-power interconnects.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.3390/app11030915">doi:10.3390/app11030915</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/3exmexrgr5gttbxlscdvyyxuti">fatcat:3exmexrgr5gttbxlscdvyyxuti</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20210129033549/https://res.mdpi.com/d_attachment/applsci/applsci-11-00915/article_deploy/applsci-11-00915-v2.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/4f/52/4f52854d7d5c9f20da3f0258e854c437f42bd73b.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.3390/app11030915"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="unlock alternate icon" style="background-color: #fb971f;"></i> mdpi.com </button> </a>

Intsim: a CAD tool for optimization of multilevel interconnect networks

Deepak C. Sekar, Azad Naeemi, Reza Sarvari, Jeffrey A. Davis, James D. Meindl
<span title="">2007</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/tadj4kfdtfdjfhulrlnjm4vb4i" style="color: black;">Computer-Aided Design (ICCAD), IEEE International Conference on</a> </i> &nbsp;
(iii) A future 22nm 8 GHz 96M gate logic core's power, die size and optimal multilevel interconnect architecture are predicted.  ...  (ii) When compared to a 22nm low power logic core with copper interconnects, a similar logic core with carbon nanotube interconnects could reduce power by 25% and die area by 27%, or increase frequency  ...  Since the die area of a design depends on both interconnect routing and gate sizing considerations, an extension of the above explained methodology can be used to predict die area of a circuit block or  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/iccad.2007.4397324">doi:10.1109/iccad.2007.4397324</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/iccad/SekarNSDM07.html">dblp:conf/iccad/SekarNSDM07</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/gkvhaxzkubehdaezswu6eibcbu">fatcat:gkvhaxzkubehdaezswu6eibcbu</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20120620063609/http://www.monolithic3d.com:80/uploads/6/0/5/5/6055488/d_c_sekar_iccad_2007.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/ea/d2/ead2511bb1990dba63dff00f8973296ea49221b5.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/iccad.2007.4397324"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Electrothermal engineering in the nanometer era

Kaustav Banerjee, Sheng-Chih Lin, Navin Srivastava
<span title="">2006</span> <i title="ACM Press"> Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC &#39;06 </i> &nbsp;
First, effects at the micro scale--in interconnects and devices and their implications for performance, reliability and design are discussed.  ...  This paper will provide a broad overview of various ET effects in nanoscale VLSI and highlight both technology and design choices that are thermally-aware.  ...  Additionally, due to a 5X increase of total leakage power every generation [42] , the design constraint based on leakage power may soon limit the yield.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1118299.1118360">doi:10.1145/1118299.1118360</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/62pp7iver5dudjt4i54tkrehlu">fatcat:62pp7iver5dudjt4i54tkrehlu</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170810105308/http://nrl.ece.ucsb.edu/sites/default/files/sites/default/papers/ASPDAC_2006.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/47/b0/47b0b311cd17b44902a3aaa139d711150da6d1a6.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1118299.1118360"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

Call for Papers

<span title="">2006</span> <i title="IEEE"> 7th International Symposium on Quality Electronic Design (ISQED&#39;06) </i> &nbsp;
Analysis, modeling, and abstraction of manufacturing process parameters and effects for highly predictable silicon performance.  ...  Design metrics, methodologies and flows for custom, semi-custom, ASIC, FPGA, RF, memory, networking circuit, etc. with emphasis on quality. Design metrics and quality standards for SoC, and SiP.  ...  Planning tools for predictable high-current, low-voltage power distribution. Reliable clock tree generation and clock distribution methodologies for Gigahertz designs.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/isqed.2006.32">doi:10.1109/isqed.2006.32</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/fnsiegfjcrb4lhgwqogh64kbq4">fatcat:fnsiegfjcrb4lhgwqogh64kbq4</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170830162806/https://www.computer.org/csdl/proceedings/isqed/2006/2523/00/25230821.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/3e/ea/3eea6d53edec3f32a03f5cf4f0ae1ad1deefa16f.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/isqed.2006.32"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Accurate Predictive Interconnect Modeling for System-Level Design

Luca P. Carloni, Andrew B. Kahng, Swamy V. Muddu, Alessandro Pinto, Kambiz Samadi, Puneet Sharma
<span title="">2010</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/uqbr2omxsbdgtaxslmblka2nnu" style="color: black;">IEEE Transactions on Very Large Scale Integration (vlsi) Systems</a> </i> &nbsp;
We propose new accurate predictive models for the delay, power, and area of buffered interconnects to enable a more effective system-level design exploration with existing and future nanometer technology  ...  We integrate our models in the COSI-OCC communication synthesis infrastructure and show how they impact the feasibility and optimality of the network-on-chip architectures that are synthesized by this  ...  Section IV describes TAP-low, which is a combination of TAP and a low-power-state-based technique.Section V presents the experimental methodology and results.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tvlsi.2009.2014772">doi:10.1109/tvlsi.2009.2014772</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/foets72m7rg5xg6ol7e7rnsn3m">fatcat:foets72m7rg5xg6ol7e7rnsn3m</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20100624005815/http://www.cs.columbia.edu/%7Eluca/research/nocs_TransVLSI10.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/9b/e4/9be41dc825f06796cb01cdb52137a03c0da90ac4.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tvlsi.2009.2014772"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Proceedings of the ASP-DAC 2003. Asia and South Pacific Design Automation Conference 2003 (Cat. No.03EX627)

<span title="">2003</span> <i title="IEEE"> Conference of Asia and South Pacific Design Automation 2003 </i> &nbsp;
Prediction of the Impact of On-chip Inductance on Interconnect Delay Using Electrical and Physical Parameters Takashi Sato, Toshiki Kanamoto, Atsushi Kurokawa, Yoshiyuki Kawakami, Hiroki Oka, Tomoyashi  ...  Logic 366 370 374 Session 4D Design Methodologies for Leading Edge Low-Power Design ~~ 385 Gu ..............................................................................  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/aspdac.2003.1194983">doi:10.1109/aspdac.2003.1194983</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/obdbe4dwivgsfpbeuvb7s73fpe">fatcat:obdbe4dwivgsfpbeuvb7s73fpe</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170830044255/http://web.cecs.pdx.edu/~mperkows/CLASS_573/Asynchr_Febr_2007/01194983.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/9a/9d/9a9d9fd068e38ce595a3c6309bbe1f25970c804d.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/aspdac.2003.1194983"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Networks-on-Chip: Emerging Research Topics and Novel Ideas

Davide Bertozzi, Shashi Kumar, Maurizio Palesi
<span title="">2007</span> <i title="Hindawi Limited"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/dgruxbbpd5bedpkwsg4wfnroya" style="color: black;">VLSI design (Print)</a> </i> &nbsp;
Through an aggressive path segmentation, NoCs loosen the delay bottleneck of on-chip interconnects and improve design predictability.  ...  At the same time, design predictability of global chip-wide structures (like some state-of-the-art system interconnects) is increasingly jeopardized.  ...  Through an aggressive path segmentation, NoCs loosen the delay bottleneck of on-chip interconnects and improve design predictability.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1155/2007/26454">doi:10.1155/2007/26454</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/xqa4mh54fjcjfesipyeqkevrw4">fatcat:xqa4mh54fjcjfesipyeqkevrw4</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170808031931/http://www.diit.unict.it/users/mpalesi/DOWNLOAD/vlsid07.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/24/a8/24a877011d767e9aba5113dade0a61baab7c66fe.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1155/2007/26454"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="unlock alternate icon" style="background-color: #fb971f;"></i> hindawi.com </button> </a>

Limitations and challenges of computer-aided design technology for CMOS VLSI

R.E. Bryant, Kwang-Ting Cheng, A.B. Kahng, K. Keutzer, W. Maly, R. Newton, L. Pileggi, J.M. Rabaey, A. Sangiovanni-Vincentelli
<span title="">2001</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/yfvtieuumfamvmjlc255uckdlm" style="color: black;">Proceedings of the IEEE</a> </i> &nbsp;
A second limitation is that the effectiveness of the design process is determined by its context-the design methodologies and flows we employ, and the designs that we essay-perhaps more than by its component  ...  One limitation is that the integrated circuit (IC) design process-like any other design process-involves practical tradeoffs among multiple objectives.  ...  As one example, circuit design styles (based on programmable logic arrays (PLAs), or power-signal-signal-ground (PSSG) style-shielded interconnect design, etc.) can improve timing predictability by enforcing  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/5.915378">doi:10.1109/5.915378</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/jocv62sorfbnjp53u7b76j4mdi">fatcat:jocv62sorfbnjp53u7b76j4mdi</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20040420211035/http://www.ece.osu.edu:80/~jinh/cmos_cad.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/fc/c0/fcc061db4da002423266e348195072d6b0166adc.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/5.915378"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Scanning the issue - Interconnections - addressing the next challenge of IC technology (part II: design, characterization, and modeling)

J.E. Schutt-Aine, Sung-Mo Kang
<span title="">2001</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/yfvtieuumfamvmjlc255uckdlm" style="color: black;">Proceedings of the IEEE</a> </i> &nbsp;
His research interests include VLSI design methodologies and optimization for performance, reliability and manufacturability, modeling and simulation of semiconductor devices and circuits, high-speed optoelectronic  ...  where he worked on transistor modeling. During his graduate studies at UIUC, he held summer positions at GTE Network Systems in Northlake, IL.  ...  With the current trends toward low power, speed and signal integrity have become harder to achieve and pose serious problems to designers.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/jproc.2001.929645">doi:10.1109/jproc.2001.929645</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/uz5t5stfsjeapklufbbheldeoe">fatcat:uz5t5stfsjeapklufbbheldeoe</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20150923091712/http://ieeexplore.ieee.org/ielx5/5/20097/00929645.pdf?tp=&amp;arnumber=929645&amp;isnumber=20097" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/f1/b2/f1b2c355c1ba6fc810c08e74a356ee2473ff6548.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/jproc.2001.929645"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Exploring compromises among timing, power and temperature in three-dimensional integrated circuits

Hao Hua, Chris Mineo, Kory Schoenfliess, Ambarish Sule, Samson Melamed, Ravi Jenkal, W. Rhett Davis
<span title="">2006</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/5vn6yyeefbbxtoo3uhwxwjwtme" style="color: black;">Proceedings of the 43rd annual conference on Design automation - DAC &#39;06</a> </i> &nbsp;
In order to help understand this trade-off, physical design experiments were performed on a low-power and a high-performance design in an existing 3DIC technology.  ...  Each design was partitioned and routed with varying numbers of tiers and thermal-via densities. A thermal-analysis methodology is developed to predict the final performance.  ...  Thanks to MIT Lincoln Labs for providing access to their FD-SOI library and for their aid in developing our design kit.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1146909.1147161">doi:10.1145/1146909.1147161</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/dac/HuaMSSMJD06.html">dblp:conf/dac/HuaMSSMJD06</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/n5b5v7rxtzajtlo7gsc4ywyr6i">fatcat:n5b5v7rxtzajtlo7gsc4ywyr6i</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20120901084656/http://www.ece.ncsu.edu:80/muse/papers/DAC2006.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/d5/a5/d5a58f6fb17d4c4cbf0aa61c0b1b8bf29d06681c.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1146909.1147161"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>
&laquo; Previous Showing results 1 &mdash; 15 out of 88,151 results