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Product On-Chip Process Compensation for Low Power and Yield Enhancement
[chapter]
2010
Lecture Notes in Computer Science
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This paper aims at introducing a reliable on-chip process compensation flow for industrial integrated systems. ...
The proposed design flow includes efficient methodologies to gather/sort on-chip process data but also post-silicon tuning strategies and validation methods at both design and test steps. ...
On Chip Performance Monitors To allow on-chip performance monitoring, a set of specific oscillators were designed to monitor individually the performances of NMOS and PMOS in terms of speed and leakage ...
doi:10.1007/978-3-642-11802-9_29
fatcat:vqj74wa7sfd3rpbcerglctj334
A 135mV 0.13μW process tolerant 6T subthreshold DTMOS SRAM in 90nm technology
2008
2008 IEEE Custom Integrated Circuits Conference
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Cell stability and tolerance to process variation are of primary importance in subthreshold SRAMs. We propose a DTMOS based 6T SRAM suitable for subthreshold operation. ...
The proposed SRAM achieves 200% improvement in read static noise margin at iso-area compared to the conventional 6T SRAM at a supply voltage of 200mV. ...
Fig. 3 (b) shows one possible layout of the pDT cell. Due to separation of body contacts for PMOS devices, the pDT cell requires 78% larger area than the standard CMOS cell in 90nm process. ...
doi:10.1109/cicc.2008.4672109
dblp:conf/cicc/HwangR08
fatcat:hxjvhd4lcvfz3cqq437ewvbu7e
Ultra-low-power DLMS adaptive filter for hearing aid applications
2003
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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To validate the robust operation of subthreshold logics, a 0.35 m, 23.1 kHz, 21.4 nW, 8 8 carry save array multiplier test chip was fabricated where an adaptive body biasing scheme is used for compensating ...
The test chip showed stable operation at a supply voltage of 0.30 V, which is even lower than the threshold voltages of the pMOS (0.82 V) and nMOS (0.67 V) transistors. ...
The compensation scheme is based on variable threshold CMOS (VTCMOS) where a leakage current monitor (LCM) detects the PVT variations and a self-substrate biasing (SSB) circuit applies the appropriate ...
doi:10.1109/tvlsi.2003.819573
fatcat:tzde54ybkbblxlshni5hlit6f4
A Reactive and On-Chip Sensor Circuit for NBTI and PBTI Resilient SRAM Design
2020
Electronics
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The proposed sensor-based adaptive technique compensates for the variation due to PV and aging using the body-bias-voltage-generator circuit. ...
Simulation experiments for three and ten-year stress have been performed. ...
Acknowledgments: We thank our colleagues from KETI and KEIT who provided insight and expertise that greatly assisted the research and greatly improved the manuscript. ...
doi:10.3390/electronics9020326
fatcat:nkcio7xnejdepaxoqfasm5xcky
Technology Variability From a Design Perspective
2011
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
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Increased variability in semiconductor process technology and devices requires added margins in the design to guarantee the desired yield. ...
Variability is characterized with respect to the distribution of its components, its spatial and temporal characteristics and its impact on specific circuit topologies. ...
Radu Zlatanovici, Changhwan Shin, Lynn Wang, Jason Tsai, Kenneth Duong, and Lauren Jones. ...
doi:10.1109/tcsi.2011.2165389
fatcat:jofyzmwehrgtvcmpddudtizwoe
Tbulk-BICS: A Built-In Current Sensor Robust to Process and Temperature Variations for Soft Error Detection
2008
IEEE Transactions on Nuclear Science
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Each sensor is controlled by a set of trimming bits that can be used to attune the sensitivity of the sensor compensating process and temperature variations. ...
area overhead. ...
Each N-BICS and P-BICS can monitor a certain silicon area that contains a number of NMOS and PMOS transis- tors, respectively. ...
doi:10.1109/tns.2008.920426
fatcat:6xjpvmxw45banhhdhsl2xcxnzy
sBSNN: Stochastic-Bits Enabled Binary Spiking Neural Network with On-Chip Learning for Energy Efficient Neuromorphic Computing at the Edge
[article]
2020
arXiv
pre-print
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CMOS process, to achieve efficient on-chip training and inference for image recognition tasks. ...
one-bit precision for power-efficient and memory-compressed neuromorphic computing. ...
Also, the PMOS and NMOS sizing, and bit-precision for the respective codes can be tuned based on the application requirements.
B. ...
arXiv:2002.11163v1
fatcat:c457skonkfauhg2zmht7ereuqy
Design of a wide-band frequency synthesizer based on TDC and DVC techniques
2002
IEEE Journal of Solid-State Circuits
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A wide-band frequency synthesizer based on time-todigital (TDC) and digital-to-voltage (DVC) conversion techniques is proposed here. ...
A test chip is designed and fabricated in 0.6-m CMOS single-poly triple-metal process. Here, the novel DVC circuit is realized by tristate inverters, where the resolution can achieve 0.2 mV. ...
., for many fruitful suggestions in implementations. The Multiple-Project Chip (MPC) support from NSC/CIC is acknowledged as well. ...
doi:10.1109/jssc.2002.803011
fatcat:kjhz5h5xzjasrcfjyz4kasqvwa
CMOS Leakage and Power Reduction in Transistors and Circuits: Process and Layout Considerations
2012
Journal of Low Power Electronics and Applications
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For achieving this power reduction, solutions based on process-device and process-integration improvements, on careful layout modification as well as on circuit design are in use. ...
For standard cells and SRAMs cells, leakage aware layout optimization techniques considering transistor configuration, stressors, line-edge-roughness and more are presented. ...
Israel Rotstein for fruitful discussions, and to O. Menadeva and S. Levi from Applied Materials, Israel for the design aware experiments reviewed in this paper. ...
doi:10.3390/jlpea2010001
fatcat:m67kazgmfbcwvktbtqurnevh74
Standby supply voltage minimization for deep sub-micron SRAM
2005
Microelectronics Journal
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This paper models the DRV of a standard low leakage SRAM module as a function of process and design parameters, and analyzes the SRAM cell stability when V DD approaches DRV. ...
Due to a large on-chip variation, DRV of the 4 KB SRAM module ranges between 60 and 390 mV. ...
The authors would also like to thank to Professor Seth Sanders and Dr. Bhusan Gupta for their enlightening technical advice. ...
doi:10.1016/j.mejo.2005.03.003
fatcat:hupcro7gh5d4dpg4kznatc6wt4
Physically clustered forward body biasing for variability compensation in nanometer CMOS design
2009
2009 Design, Automation & Test in Europe Conference & Exhibition
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Nanometer CMOS scaling has resulted in greatly increased circuit variability, with extremely adverse consequences on design predictability and yield. ...
Adaptive Body Bias (ABB) is one of the most successful tuning "knobs" in use today in high-performance custom design. ...
Note that our methodology works on standard cell based designs and we apply body bias voltage at standard cell row level granularity. ...
doi:10.1109/date.2009.5090650
dblp:conf/date/SathanurPBMM09
fatcat:ne6k7zfitbdgjl47obcmxvu6a4
Statistical reliability analysis of NBTI impact on FinFET SRAMs and mitigation technique using independent-gate devices
2012
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures - NANOARCH '12
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Dynamic NBTI stress on SRAM cells is modeled by using stochastic input signals. ...
Our simulations conducted at an accelerated temperature 125 • C for 10 8 seconds (∼3 years) indicate that a V th compensation of 0.2V can almost preserve the WRITE and HOLD stability of the fresh device ...
IG-FinFET Based V th Compensation Scheme for SRAM Cells In order to minimize the damage caused by NBTI and increase the read stability of the SRAM cell, in this section we demonstrate an NBTI mitigation ...
doi:10.1145/2765491.2765512
dblp:conf/nanoarch/0002CF12
fatcat:p5edthdvyvbsbng2fu7gkiyc5q
Process Variations and Process-Tolerant Design
2007
20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)
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This article analyzes the impact of process parameter variations on logic circuits and memory and focuses on some major works in the area of process-tolerant design methodology at circuiffarchitecture ...
While CMOS technology has served semiconductor industry marvelously (by allowing nearly exponential increase in performance and device integration density), it faces some major roadblocks at sub-90nm process ...
A bidirectional adaptive body bias (ABB) technique is used to compensate for die-to-die parameter variations in [IS] by applying an optimum PMOS and nMOS body bias voltage to each die. ...
doi:10.1109/vlsid.2007.131
dblp:conf/vlsid/BhuniaMR07
fatcat:haw2cidqhng7ngucgvwiftnsza
Wide-supply-range all-digital leakage variation sensor for on-chip process and temperature monitoring
2014
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)
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This paper proposes an all-digital on-chip circuit to monitor leakage current variations of both of the nMOSFET and pMOS-FET independently. ...
The proposed technique enables area-efficient and low-cost implementation thus can be used in product chips for applications such as dynamic energy and thermal management, testing and post-silicon tuning ...
Digital approach using standard cells fails to give us area-efficiency to implement local variability monitors [27] . ...
doi:10.1109/asscc.2014.7008856
dblp:conf/asscc/MahfuzulSIO14
fatcat:klhgucltnbcx5cwsynq46if4p4
Variation in Transistor Performance and Leakage in Nanometer-Scale Technologies
2008
IEEE Transactions on Electron Devices
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This paper then illustrates the impact of the observed variability on SRAM, analog and digital circuit blocks used in system-on-chip designs. ...
Different approaches for minimizing transistor variation and mitigating its impact on product performance and yield are also described. ...
The first is included as part of a full reticle characterization vehicle (CV) test chip for characterizing the impact of front end of the line processing on yield and transistor performance and variability ...
doi:10.1109/ted.2007.911351
fatcat:i5eigzxd7ba4fgocgh2vcfbwtq
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