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An Empirical Methodology for Power Analysis of CMOS Integrated Circuits

Momcilo V. Krunic, Ivan Povazan, Jelena V. Kovacevic, Vlado M. Krunic
2017 Elektronika ir Elektrotechnika  
Therefore, an empirical methodology for determination of power and energy dissipation may provide valuable information to IC designers, as well as software developers, which could impact design process  ...  1 Abstract-Energy consumption is becoming one of the most significant aspects of CMOS Integrated Circuits (IC), especially for those applied in embedded devices whose autonomy depends upon battery lifespan  ...  Leakage current of CMOS IC -Istat could be defined as a sum of leakage currents of each individual CMOS transistor -Ileak that is under the voltage Fig. 4 . 4 Dynamic currents of CMOS inverter in two  ... 
doi:10.5755/j01.eie.23.5.19242 fatcat:wr4odowbvbd5pbn7ngo634fjqy

Design of Low Power Consumption Inverter

Mahesh Bhat K
2020 International Journal for Research in Applied Science and Engineering Technology  
This increased the leakage power and continues to be one of the major issues in the design of CMOS circuits in the nanometer technology.  ...  It is observed that the proposed design reduces power consumption by about 22%.  ...  The static power dissipation is because of the leakage current when the circuit in standby mode. The Dynamic power is due to switching and short-circuit power.  ... 
doi:10.22214/ijraset.2020.31227 fatcat:tijf3utbvbb7lmmwlipuhty4xe

Long-term Electro-Magnetic Robustness of Integrated Circuits: EMRIC research project

S. Ben Dhia, A. Boyer
2013 Microelectronics and reliability  
This paper presents the scientific achievements of EMRIC project that aimed at developing a new research activity which mixes EMC and IC reliability.  ...  This project contributes to improve the electromagnetic robustness (EMR) of integrated circuits over the full life-time of the electronic system, with a special emphasis on deep submicron technology.  ...  As explained in part 4.2, predicting the drift of IC emission relies on an accurate modeling of the evolution of dynamic current consumption.  ... 
doi:10.1016/j.microrel.2013.08.016 fatcat:r3iukpfpujbbpk7sesqp43cxzi

Circuits and design techniques for secure ICs resistant to side-channel attacks

I. Verbauwhede, K. Tiri, D. Hwang, P. Schaumont
2006 2006 IEEE International Conference on IC Design and Technology  
The key or other sensitive information, can be guessed by monitoring the execution time, the power varia-  ...  approach has been applied to the design of an AES co-propower analysis.  ...  We will also discuss issues of side-channel resistime or the power consumption profile of the algorithm. tance when implementing ICs in future technologies.  ... 
doi:10.1109/icicdt.2006.220791 fatcat:q74mzqssunbefk5j37msqj2xhu

Design and Verification for Hierarchical Power Efficiency System (HPES) Design Techniques Using Low Power CMOS Digital Logic [chapter]

Taikyeong Jeong, Jaemyoung Lee
2006 Lecture Notes in Computer Science  
This paper presents the design implementation of digital circuit and verification method for power efficiency systems, focused on static power consumption while the CMOS logic is in standby mode.  ...  Our approach to designing reliable hardware involves techniques for hierarchical power efficiency system (HPES) design and a judicious mixture of verification method is verified by this formal refinement  ...  In addition, test circuitry is mathematically checked and formally proven not to interfere with the functionality of the IC. Exhaustive simulations and tests are employed using multiple simulations.  ... 
doi:10.1007/11758501_101 fatcat:uktamih2izghnigbypd5xt6v2i

Ultra-Low Voltage Analog IC Design: Challenges, Methods and Examples

V. Stopjakova, M. Rakus, M. Kovac, D. Arbet, L. Nagy, M. Sovcik, M. Potocny
2018 Radioengineering  
Finally, examples of basic building blocks of ultra-low voltage analog ICs designed in standard CMOS technology using such design techniques are presented.  ...  Then, design techniques and approaches to analog integrated circuits towards (ultra) low-voltage systems and applications are described.  ...  Section 3 brings an overview of design techniques and approaches to analog IC design that can be used to overcome serious limitations linked with a low value of the power supply and process fluctuations  ... 
doi:10.13164/re.2018.0171 fatcat:mrj5ku5tdrco5fhzito7irkbva

Technical Study on Low Power VLSI methods

T. Kapilachander, I.Hameem Shanavas, V. Venkataraman
2012 International Journal of Information Engineering and Electronic Business  
This paper explains about the combination of techniques used for low power approach in integrated circuits (IC) or Chip  ...  Power management is becoming an increasingly urgent problem for almost every category of design and application, as power density, measured in watts per square millimeter, rises at an alarming rate.  ...  Mainly two components determine the power consumption in a CMOS circuit Static power consumption and Dynamic power consumption, since Short Circuit Power Consumption is rarely occurred one.  ... 
doi:10.5815/ijieeb.2012.01.08 fatcat:3montcjhfrdgxdvfeq33bzuxdu


2015 Journal of Engineering Science and Technology  
Total power dissipation in CMOS circuits has become a huge challenging in current semiconductor industry due to the leakage current and the leakage power.  ...  This article reviews the relevant researches of the source or power dissipation, the mechanism to reduce the dynamic power dissipation as well as static power dissipation and an overview of various circuit  ...  Power dissipation is an important parameter in the design of CMOS ICs [1] .  ... 
doaj:1248829086604e968f8e6af5dd0fb5db fatcat:ii5cdjh5sfe35i6fzns5h3xy3a

Why is CMOS scaling coming to an END?

Nor Zaidi Haron, Said Hamdioui
2008 2008 3rd International Design and Test Workshop  
The continued physical feature size scaling of complementary Metal Oxide Semiconductor (CMOS) transistors is experiencing asperities due to several factors, and it is expected to reach its boundary at  ...  The paper also addresses alternative non-CMOS devices (i.e., nanodevices) that are potentially able to solve the CMOS problems and limitations.  ...  There are two types of power density dissipate by per unit area of integrated circuit (IC) chips namely dynamic power density and static power density [18] .  ... 
doi:10.1109/idt.2008.4802475 fatcat:2cwk4mo6xzfkvewyy7jr23pvii

A side-channel leakage free coprocessor IC in 0.18µm CMOS for embedded AES-based cryptographic and biometric processing

K. Tiri, D. Hwang, A. Hodjat, B. Lai, S. Yang, P. Schaumont, I. Verbauwhede
2005 Proceedings of the 42nd annual conference on Design automation - DAC '05  
Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption and other information that is leaked by the switching behavior of digital CMOS gates  ...  This paper describes a side-channel attack resistant coprocessor IC and its design techniques. The IC has been fabricated in 0.18µm CMOS.  ...  The fabricated IC uses Wave Dynamic Differential Logic [4] to implement dynamic differential behavior using static CMOS standard cells.  ... 
doi:10.1145/1065579.1065639 dblp:conf/dac/TiriHHLYSV05 fatcat:bwcxkoxmsnauhatixcr7okobma

A High-Speed CMOS OP Amplifier with a Dynamic Switching Bias Circuit

2013 SICE Journal of Control Measurement and System Integration  
This paper presents a high-speed CMOS operational amplifier (OP Amp) with a dynamic switching bias circuit, capable of processing video signals of over 2 MHz with decreased dissipated power.  ...  The OP Amp was designed to operate at a 10 MHz dynamic switching rate, and was shown in simulations to have a dissipated power of 66 % of conventional continuous operation.  ...  Until now, several approaches including the development of ICs working at low power supply voltages have been taken to decrease the power consumption of OP Amps.  ... 
doi:10.9746/jcmsi.6.376 fatcat:loorqe4ym5blromnhzdo5tembi

A continuous-time /spl Delta//spl Sigma/ modulator with 63-dB dynamic range and 500kHz bandwidth in 0.35/spl mu/m SOI CMOS technology

Jinhu Sun, Yi Zhang, A. Leuciuc, Yi Tian
2005 48th Midwest Symposium on Circuits and Systems, 2005.  
Modulator operates at a supply voltage of 3.3V, uses an oversampling ratio of 32 and can achieve a maximum dynamic range of 63dB (more than 10 bits) in a bandwidth of 500KHz.  ...  This paper describes the implementation of a continuous-time low-pass ∆Σ modulator in SOI CMOS technology.  ...  CONCLUSION The technology advantages of the SOI CMOS technology make it an ideal process to implement high quality, low power and area efficient mixed signal ICs.  ... 
doi:10.1109/mwscas.2005.1594156 fatcat:htfk5ij7nbgihmsxbac7ddrq2m

SC-DDPL as a Countermeasure against Static Power Side-Channel Attacks

Davide Bellizia, Riccardo Della Sala, Giuseppe Scotti
2021 Cryptography  
With the continuous scaling of CMOS technology, which has now reached the 3 nm node at production level, static power begins to dominate the power consumption of nanometer CMOS integrated circuits.  ...  Experimental results on an FPGA implementation of a compact PRESENT crypto-core show that the SC-DDPL implementation allows a great improvement of all the security metrics with respect to the standard  ...  Since the static current is correlated to the input data of CMOS cryptographic ICs, it can be considered as an additional side channel that an attacker can exploit to infer the secret keys.  ... 
doi:10.3390/cryptography5030016 fatcat:a4s63dvaybakthtk2u2e3jrm2e

A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC With Signal-Independent Delta-I Noise DfT Scheme

Georgi I. Radulov, Patrick J. Quinn, Arthur H. M. van Roermund
2015 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
To cope with the IC process variability, a unit element approach is generally employed.  ...  This paper presents a 3.5 GS/s 6-bit current-steering digital-to-analog converter (DAC) with auxiliary circuitry to assist testing in a 1 V digital 28-nm CMOS process.  ...  The power consumption of the DAC is 53 mW with an output signal current of 4.5 mA. The measured static accuracy of the B.  ... 
doi:10.1109/tvlsi.2014.2298055 fatcat:us5ncdjglfd3vk5oftocpinute

A digital design flow for secure integrated circuits

K. Tiri, I. Verbauwhede
2006 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
It successfully protects a prototype Advanced Encryption Standard (AES) IC fabricated in an 0.18-µm CMOS.  ...  This paper presents a digital very large scale integrated (VLSI) design flow to create secure power-analysis-attack-resistant ICs.  ...  It successfully protects AES on a prototype IC fabricated in an 0.18-µm CMOS.  ... 
doi:10.1109/tcad.2005.855939 fatcat:va7jilv265d53kz6jbfwfdsmye
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