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An Approach for Implementing Efficient Superscalar CISC Processors

Shiliang Hu, Ilhyun Kim, M.H. Lipasti, J.E. Smith
The Twelfth International Symposium on High-Performance Computer Architecture, 2006.  
per cycle) that is equivalent to a conventional four-wide superscalar processor. 1) The co-designed VM approach is applied to an enhanced out-of-order superscalar implementation of a CISC ISA, the x86  ...  Steady state performance is evaluated for the SPEC2000 benchmarks" and a proposed x86 implementation with complexity similar to a two-wide superscalar processor is shown to provide performance (instructions  ...  Michael Shebanow and anonymous reviewers for helpful feedback. We appreciate Dr. Ho-Seop Kim's help with the microarchitecture timing model.  ... 
doi:10.1109/hpca.2006.1598111 dblp:conf/hpca/HuKLS06 fatcat:efwudok7tbhk5fljucv6zwhjn4

Decisive aspects in the evolution of microprocessors

D. Sima
2004 Proceedings of the IEEE  
The incessant market demand for higher and higher processor performance called for a continuous increase of clock frequencies as well as an impressive evolution of the microarchitecture.  ...  parts or subsystems. 2 In order to avoid a large number of multiple references to superscalar processors in the text and in the figures, we give all references to superscalars only in Fig. 28 .  ...  Thus, the execution model of RISC processors is basically valid for CISC processors as well.  ... 
doi:10.1109/jproc.2004.837627 fatcat:lj6qx4lbojbzjgn4meo5n7f72m

Decisive Aspects in the Evolution of Microprocessors

H. Falk
2004 Proceedings of the IEEE  
Pertinent relationships constitute an underlying logical framework for the fascinating evolution of microarchitectures, which is presented in our paper.  ...  =6 6,0$ 0(0%(5 ,((( The incessant demand for higher performance has provoked a dramatic evolution of the microarchitecture of high performance microprocessors.  ...  First, CISC processors typically have a lower issue rate than RISC processors (mostly three in recent CISC processors).  ... 
doi:10.1109/jproc.2004.837615 fatcat:3liaxjrdcje3rddzxtm52kagtu

Development of efficient computational kernels and linear algebra routines for out-of-order superscalar processors

O. Bessonov, D. Fougère, B. Roux
2005 Future generations computer systems  
The obtained performance results for AMD processors are discussed in comparison with other approaches.  ...  Approaches for implementing matrix multiplication algorithms are suggested for hierarchical memory computers. Block versions of matrix multiplication and LUdecomposition algorithms are considered.  ...  Acknowledgements This work was partially supported by the Russian Foundation for Basic Research (grants 01-01-00745 and 02-01-00210).  ... 
doi:10.1016/j.future.2004.05.016 fatcat:rtfuljawdvh3pkow5a4xl5xnn4

Reducing Startup Time in Co-Designed Virtual Machines

Shiliang Hu, James E. Smith
2006 SIGARCH Computer Architecture News  
Dynamic binary translation converts code written for a conventional (legacy) ISA into optimized code for an underlying implementation-specific ISA.  ...  A Co-Designed Virtual Machine allows designers to implement a processor via a combination of hardware and software.  ...  The overall design supports a conventional (legacy) ISA, but the hardware directly supports an implementation ISA that is designed for superior performance and/or power efficiency.  ... 
doi:10.1145/1150019.1136510 fatcat:ovartktsvjcv7ciyijeke3l77e

Effect of multicycle instructions on the integer performance of the dynamically trace scheduled VLIW architecture [chapter]

Alberto Ferreira de Souza, Peter Rounce
1999 Lecture Notes in Computer Science  
Dynamically trace scheduled VLIW (DTSVLIW) architectures can be used to implement machines that execute code of current RISC or CISC instruction set architectures in a VLIW fashion, delivering instruction  ...  Introduction The classic approaches to providing ILP are VLIW and superscalar architectures.  ...  We showed it to be suitable for pipelined implementation in [5] .  ... 
doi:10.1007/bfb0100690 fatcat:oqambrinkfa5bi5kg2olahvisy

Superscalar instruction issue

D. Sima
1997 IEEE Micro  
This article focuses on superscalar instruction issue, tracing the way parallel instruction execution and issue have increased performance.  ...  C learly, instruction issue and execution are closely related: The more parallel the instruction execution, the higher the requirements for the parallelism of instruction issue.  ...  Nx586 has scalar issue for CISC instructions but a three-way superscalar core for converted RISC instructions.  ... 
doi:10.1109/40.621211 fatcat:wyqwzzvaf5axdkp45yyg354e4a

Scalable vector processors for embedded systems

C.E. Kozyrakis, D.A. Patterson
2003 IEEE Micro  
This work was supported by DARPA (DABT63-96-C-0056) and by an IBM PhD fellowship.  ...  This article advocates an alternative approach to embedded processors that provides high performance for critical tasks without sacrificing power efficiency or design simplicity.  ...  We normalize the performance for each processor to that of the MPC7455 superscalar processor.  ... 
doi:10.1109/mm.2003.1261385 fatcat:arrxeb4uk5ek3ohjheugjmxyji

Explicit Parallel Instruction Computing

Pranjal Mathur
2016 International Journal Of Engineering And Computer Science  
EPIC combines the capabilities of both Superscalars processors and VLIW processors.  ...  VLIW (Very Long Instruction Word) machines are highly parallel ILP (Instruction Level Parallelism) based architectures that offer an alternative to scalar sequential architectures like CISC/RISC.  ...  EPIC architectures can claim to combine the best attributes of superscalar processors (compatibility across implementations) and VLIW processors (efficiency since less control logic).  ... 
doi:10.18535/ijecs/v5i7.13 fatcat:nux3e66usjdkxnse3ft6xbny5y

SHA: A Design for Parallel Architectures? [chapter]

Antoon Bosselaers, René Govaerts, Joos Vandewalle
1997 Lecture Notes in Computer Science  
To enhance system performance computer architectures tend to incorporate an increasing number of parallel execution units.  ...  It will also be shown that, due to the organization of RIPEMD-160 in two independent lines, it will probably be easier for future architectures to exploit its software parallelism.  ...  particular superscalar processor as starting point, and investigated to which extent an implementation of the hashing algorithms could take advantage of that architecture.  ... 
doi:10.1007/3-540-69053-0_24 fatcat:rtzl66awnze5ta424tfxpimhse

Energy Efficient Dual Issue Embedded Processor

Hanni Lozano, Mabo Ito
2016 EAI Endorsed Transactions on Industrial Networks and Intelligent Systems  
The processor is optimized for implementation on a low cost FPGA which makes it a suitable candidate for cost sensitive embedded industrial applications.  ...  High performance superscalar embedded processors are more energy efficient than low performance scalar processors, however, they consume more power which is very limited in battery operated deeply embedded  ...  Despite the popular belief that RISC processors are more efficient than CISC processors, a recent study comparing RISC and CISC has shown that the choice of an instruction set has no impact performance  ... 
doi:10.4108/eai.1-1-2016.150814 fatcat:ilaq23afxvbmpcud6txcuux7ea

Integration of code optimization and hardware exploration for a VLIW architecture by using fuzzy control system

Xiaoyan Jia, Gerhard Fettweis
2011 2011 IEEE International SOC Conference  
To improve the system efficiency of STA, in this paper we propose a novel approach to integrate compiler techniques with architecture exploration: A fuzzy control system is implemented to help the compiler  ...  Finally, the novel approach enjoys short compilation time and less complex implementation.  ...  Background of STA processor The Superscalar architecture, a special subclass of RISCs or CISCs, enables multiple operation pipelines in order to allow multiple operations to be executed in one clock cycle  ... 
doi:10.1109/socc.2011.6085072 dblp:conf/socc/JiaF11 fatcat:67b6ngvedfhznmjh7wb7uu5uwi

45-year CPU evolution: one law and two equations [article]

Daniel Etiemble
2018 arXiv   pre-print
Moore's law and two equations allow to explain the main trends of CPU evolution since MOS technologies have been used to implement microprocessors.  ...  As the cores of multicores are implemented by superscalar (multithreaded or not) mono-processors, reducing IC by increasing the number of cores is the main technique for getting increased performance.  ...  Superscalar execution consists in issuing several instructions per clock with different approaches: a) In-order superscalar CPUs issue a group of instructions obeying defined rules per clock cycle.  ... 
arXiv:1803.00254v1 fatcat:mquk7tfhjrfz7ldokb2alpuevq

POD: A 3D-Integrated Broad-Purpose Acceleration Layer

Dong Hyuk Woo, Hsien-Hsin S. Lee, Joshua B. Fryman, Allan D. Knies, Marsha Eng
2008 IEEE Micro  
Although each PE will ideally be capable of decoding conventional CISC instructions for execution, this approach will require a large instruction decoder for each PE.  ...  For example, Tarantula, which had relatively narrow SIMD engines attached to a superscalar processor, implemented a recovery mechanism in each PE. 3 Unfortunately, this results in substantial overhead  ...  His research interests include energy-efficient many-core architecture and resourcesharing problems of multicore processors.  ... 
doi:10.1109/mm.2008.58 fatcat:jbjoos2zqzet3eiplzobtyeyxe

A Tale of Two Processors: Revisiting the RISC-CISC Debate [chapter]

Ciji Isen, Lizy K. John, Eugene John
2009 Lecture Notes in Computer Science  
This can easily allow CISC processors to approach RISC performance. However, CISC ISAs do have the additional burden of translating instructions to micro-operations.  ...  Our study points to the fact that if aggressive micro-architectural techniques for ILP and high performance can be carefully applied, a CISC ISA can be implemented to yield similar performance as RISC  ...  Indukuru and Lorena Pesantez at IBM Austin for their guidance. The authors are supported in part by NSF grant 0702694, and an IBM Faculty award.  ... 
doi:10.1007/978-3-540-93799-9_4 fatcat:pdryklrmnbgatn47irpnwgvjdy
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