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Analytical approaches for performance evaluation of networks-on-chip

Abbas Eslami Kiasari, Axel Jantsch, Marco Bekooij, Alan Burns, Zhonghai Lu
2012 Proceedings of the 2012 international conference on Compilers, architectures and synthesis for embedded systems - CASES '12  
This tutorial reviews four popular mathematical formalismsdataflow analysis, schedulability analysis, network calculus, and queueing theory -and how they have been applied to the analysis of Network-on-Chip  ...  We review the basic concepts and results of each formalism and provide examples of how they have been used in on-chip communication performance analysis.  ...  INTRODUCTION In modern system-on-chip (SoC), the on-chip communication infrastructure or network-on-chip (NoC) is a dominant factor for design, validation and performance analysis.  ... 
doi:10.1145/2380403.2380442 dblp:conf/cases/KiasariJBBL12 fatcat:kc2ehewdzncahibi735ybenbx4

A Transferable Approach for Partitioning Machine Learning Models on Multi-Chip-Modules [article]

Xinfeng Xie, Prakash Prabhu, Ulysse Beaugnon, Phitchaya Mangpo Phothilimthana, Sudip Roy, Azalia Mirhoseini, Eugene Brevdo, James Laudon, Yanqi Zhou
2021 arXiv   pre-print
Multi-Chip-Modules (MCMs) reduce the design and fabrication cost of machine learning (ML) accelerators while delivering performance and energy efficiency on par with a monolithic large chip.  ...  The architectural choices we make for the policy network allow us to generalize across different ML graphs.  ...  The evaluation with an analytical model is orders of magnitude faster than evaluating the samples on real chips.  ... 
arXiv:2112.04041v1 fatcat:2m64g7rdabevdpoc4xi6io6fa4

Improving Performance Estimation for FPGA-based Accelerators for Convolutional Neural Networks [article]

Martin Ferianc, Hongxiang Fan, Ringo S. W. Chu, Jakub Stano, Wayne Luk
2020 arXiv   pre-print
to a standard analytic method in leave-one-out cross-validation.  ...  This work introduces a novel method for fast and accurate estimation of latency based on a Gaussian process parametrised by an analytic approximation and coupled with runtime data.  ...  We thank Yann Herklotz, Alexander Montgomerie-Corcoran and ARC'20 reviewers for insightful suggestions.  ... 
arXiv:2002.00190v1 fatcat:uae5gswytvairmrgfphitpaxwi

An Effective Overlap Removable Objective for Analytical Placement

Syota KUWABARA, Yukihide KOHIRA, Yasuhiro TAKASHIMA
2013 IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences  
In this paper, we propose Overlap Removable Area as an overlap evaluation method for an analytical placement method.  ...  Experiments show that the proposed evaluation method is effective for removing overlap in the analytical placement method.  ...  In this paper, we propose Overlap Removable Area as an overlap evaluation method for an analytical placement method.  ... 
doi:10.1587/transfun.e96.a.1348 fatcat:jszihuroefej5d3lagkjun5pru

An analytical model for on-chip interconnects in multimedia embedded systems

Yulei Wu, Geyong Min, Dakai Zhu, Laurence T. Yang
2013 ACM Transactions on Embedded Computing Systems  
Driven by the motivation of evaluating on-chip interconnects in multimedia embedded systems, a new analytical model is proposed to investigate the performance of the fat-tree based on-chip interconnection  ...  The traffic pattern has significant impact on the performance of network-on-chip. Many recent studies have shown that multimedia applications can be supported in on-chip interconnects.  ...  [Moadeli et al. 2010] have proposed an analytical model to evaluate the performance of ring-based on-chip interconnects.  ... 
doi:10.1145/2536747.2536751 fatcat:ddhwx7pllnc2lgmrhlrqix6qjy

A Study on Performance Modelling and Analysis of Network on Chip under M-Port N-Tree Bursty Traffic

A. Malathi
2016 International Journal Of Engineering And Computer Science  
Networks on Chip (NoC) have been proposed as a solution to mitigate complex on-chip communication problems for complex SoCs.  ...  Having developed an efficient analytical tool to capture the traffic behaviour with a higher accuracy, in the next step, the research focuses on the effect of topology on the performance of NoCs.  ...  CONCLUSION This analytical model was developed and implemented to evaluate the performance of network on-chip under bursty traffic. The bursty traffic is modeled by the wellknown MMPP.  ... 
doi:10.18535/ijecs/v5i10.38 fatcat:si4subjxdvbwxkj5rokzmv6cga

Performance evaluation and design tradeoffs of on-chip interconnect architectures

M. Bakhouya, S. Suboh, J. Gaber, T. El-Ghazawi, S. Niar
2011 Simulation modelling practice and theory  
Network-on-Chip (NoC) has been proposed as an alternative to bus-based schemes to achieve high performance and scalability in System-on-Chip (SoC) design.  ...  Performance analysis and evaluation of on-chip interconnect architectures are widely based on simulations, which become computationally expensive, especially for large-scale NoCs.  ...  In section 2, we summarize the existing work on performance analysis methods proposed for evaluating on-chip interconnects.  ... 
doi:10.1016/j.simpat.2010.10.008 fatcat:dpwadk5mljdj5nggxtg5oknyce

Efficient Modeling of Crosstalk Noise on Power Distribution Networks for Contactless 3-D ICs

Ioannis A. Papistas, Vasilis F. Pavlidis
2018 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
Thus, an efficient, scalable, and accurate method for 18 the analysis of the crosstalk effects due to inductive links is 19 provided, without resorting on computationally expensive and 20 time consuming  ...  Thus, an efficient, scalable, and accurate method for 18 the analysis of the crosstalk effects due to inductive links is 19 provided, without resorting on computationally expensive and 20 time consuming  ...  ANALYTIC MUTUAL INDUCTANCE MODELLING 150 A closed-form model for the evaluation of the mutual 151 inductance between an on-chip inductor and a loop of the 152 power distribution network is presented  ... 
doi:10.1109/tcsi.2018.2791498 fatcat:wncu76nhzjgobbpekkosv3o2le

Performance evaluation of network processor architectures: combining simulation with analytical estimation

Samarjit Chakraborty, Simon Künzli, Lothar Thiele, Andreas Herkersdorf, Patricia Sagmeister
2003 Computer Networks  
The designs of most systems-on-a-chip (SoC) architectures rely on simulation as a means for performance estimation.  ...  None of the known performance evaluation methods for network processors have been positioned from this perspective.  ...  Acknowledgements The work presented in this paper was partly supported by the National Competence Center in Research on Mobile Information and Communication Systems (NCCR-MICS), a center supported by the  ... 
doi:10.1016/s1389-1286(02)00454-1 fatcat:5dj74jijbfg6jkho6sr2f6n76e

System-level performance analysis of multiprocessor system-on-chips by combining analytical model and execution time variation

Sungchan Kim, Soonhoi Ha
2014 Microprocessors and microsystems  
Our approach consists of two techniques: (1) analytical model of on-chip crossbar-based communication architectures and (2) enumeration of task-level execution time variations for a target application.  ...  While a simulation is commonly performed for performance evaluation of an MPSoC, it often suffers from a lengthy run time as well as poor performance coverage due to limited input stimuli or their ad hoc  ...  Hence, more communication requirements are imposed on on-chip networks, which, in turn, significantly affects the performance of an MPSoC.  ... 
doi:10.1016/j.micpro.2014.02.003 fatcat:wsonxvepd5gfthhxp5ehlebrma

Analysis of Delay Time Distributions in Multistage Interconnection Networks Considering Multicast Traffic

Marcus Brenner, Armin Zimmermann
2008 2008 Seventh IEEE International Symposium on Network Computing and Applications  
scenarios: distribution of delay times, for which no analytically tractable exact method exists.  ...  In order to achieve suitable solutions when designing such networks to fit a given task, performance evaluation plays a crucial part.  ...  In the following, our focus will be on analytical performance evaluation and its use.  ... 
doi:10.1109/nca.2008.35 dblp:conf/nca/BrennerZ08 fatcat:sxxjabrp3rfjfanedgbtzqws54

Reliability and Performance Evaluation of Fault-aware Routing Methods for Network-on-Chip Architectures (RESEARCH NOTE)

2014 International Journal of Engineering  
However, for performance evaluation, we conduct extensive simulations on different applications.  ...  To demonstrate the effectiveness of these methods, we propose an analytical approach for reliability assessment based on combinatorial reliability models to show the effect of fault-aware routing algorithms  ...  INTRODUCTION 1 The advent of complex systems such as Network-on-Chip (NoC) based on Multi-Processor Systems-on-a-Chip (MPSoC); with an increase in vulnerability of integrated circuits to environmental  ... 
doi:10.5829/idosi.ije.2014.27.04a.01 fatcat:ncwqlw6zxvefvpukfubz4as4pq

Multi-Objective Genetic optimized multiprocessor SoC design

Mohammad Arjomand, Hamid Sarbazi-Azad, S. Hamid Amiri
2008 2008 International Symposium on System-on-Chip  
In this paper, we introduce a new Multi-Objective Genetic Algorithm (MOGA) for mapping a given set of intellectual property onto a Network-on-Chip architecture such that for a specific application total  ...  Experimental results show that the proposed algorithm is very fast which results in a new approach for mapping MPSoC cores on chip. I.  ...  On-chip design has more limits on resources which impose constraints on design strategies. Power dissipation issues have grown to such an importance that now constraints total chip performance.  ... 
doi:10.1109/issoc.2008.4694887 dblp:conf/issoc/ArjomandSA08 fatcat:kdcgmqi4yzanpbzo5anoerifoy

NoCIC

Vishak Venkatraman, Andrew Laffely, Jinwook Jang, Hempraveen Kukkamalla, Zhi Zhu, Wayne Burleson
2004 Proceedings of the 2004 international workshop on System level interconnect prediction - SLIP '04  
Performance and power of on-chip interconnects in the nanometer realm have been an increasing source of concern to designers.  ...  Network-on-Chip (NoC) structures have been proposed as a solution to achieve efficient and reliable communication.  ...  Network-on-Chip (NoC) architectures have been proposed, in part, as a method for dealing with interconnect difficulties.  ... 
doi:10.1145/966747.966762 dblp:conf/slip/VenkatramanLJKZB04 fatcat:62d6q5kqt5btvk7rxhozdmu4za

NoCIC

Vishak Venkatraman, Andrew Laffely, Jinwook Jang, Hempraveen Kukkamalla, Zhi Zhu, Wayne Burleson
2004 Proceedings of the 2004 international workshop on System level interconnect prediction - SLIP '04  
Performance and power of on-chip interconnects in the nanometer realm have been an increasing source of concern to designers.  ...  Network-on-Chip (NoC) structures have been proposed as a solution to achieve efficient and reliable communication.  ...  Network-on-Chip (NoC) architectures have been proposed, in part, as a method for dealing with interconnect difficulties.  ... 
doi:10.1145/966759.966762 fatcat:e5y4tlhxmvgpfkz3adz3qwqffu
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