A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2019; you can also visit the original URL.
The file type is application/pdf.
Filters
An all-digital phase-locked loop with a PGTA-based TDC and a 0.6-V DCO
2018
IEICE Electronics Express
Preserved Fulltext
An all-digitally phase-locked loop (ADPLL) with a pipeline time-to-digital converter (TDC) is proposed in this paper. ...
The TDC employs a programmable-gain time amplifier (PGTA) to achieve two-step time quantization. A compensator is used to correct the gain error of the PGTA. ...
The ADPLL consumed a total power of 4.8 mW at a 1.2-V supply, except the DCO that worked at a 0.6-V supply. ...
doi:10.1587/elex.15.20180889
fatcat:hl4tqp5qibfojhmvvyeinvwcx4