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An all-digital phase-locked loop with a PGTA-based TDC and a 0.6-V DCO

Zixuan Wang, Hao Ding, Hao Xu, Cong Zhang, Shanwen Hu, Xincun Ji, Xiaojuan Xia, Zhikuang Cai
2018 IEICE Electronics Express  
An all-digitally phase-locked loop (ADPLL) with a pipeline time-to-digital converter (TDC) is proposed in this paper.  ...  The TDC employs a programmable-gain time amplifier (PGTA) to achieve two-step time quantization. A compensator is used to correct the gain error of the PGTA.  ...  The ADPLL consumed a total power of 4.8 mW at a 1.2-V supply, except the DCO that worked at a 0.6-V supply.  ... 
doi:10.1587/elex.15.20180889 fatcat:hl4tqp5qibfojhmvvyeinvwcx4