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An all-digital de-skew clock generator for arbitrary wide range delay
2010
2010 IEEE Asia Pacific Conference on Circuits and Systems
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An all-digital de-skew clock generator for arbitrary wide range delay is proposed to minimize the instability of the clock settling while achieving fast locking time. ...
Keywords-De-skew clock generator, delay-locked loop (DLL), synchronous mirror delay (SMD). ...
The authors would like to thank Chip Implementation Center (CIC) for chip fabrication. ...
doi:10.1109/apccas.2010.5774895
dblp:conf/apccas/FongHCL10
fatcat:6gd3vza3dnawti66p5c5exe5im
An N/M-Ratio All-Digital Clock Generator with a Pseudo-NMOS Comparator-Based Programmable Divider
2022
Electronics
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A multiplying delay-locked loop (MDLL)-based all-digital clock generator with a programmable N/M-ratio frequency multiplication capability for digital SoC is presented. ...
Fabricated in a 0.13-µm 1.2-V CMOS process, the proposed digital MDLL clock generates fully de-skewed output clock frequencies from 0.3 to 1.137 GHz with programmable N/M ratios of N = 1~32 and M = 1~16 ...
Thus, the proposed programmable N/M-ratio MDLL clock generator is suitable for low-power memory and SoC design requiring de-skewed and wide-range dynamic frequency scaling. ...
doi:10.3390/electronics11020261
fatcat:7rw2n4edcvcyvdb3zfuddd2hl4
A New Interface Technique for the Acquisition of Multiple Multi-Channel High Speed ADCs
2008
IEEE Transactions on Nuclear Science
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We detail the proposed method and show an implementation where a single field programmable gate array is used to collect data from twenty four 12-bit ADC channels clocked at 20 MHz. ...
Index Terms-Field Programmable Gate Arrays, high speed analog to digital converters, source synchronous interfaces. ...
ACKNOWLEDGMENT The author wishes to thank the main contributors to the design of the time projection chamber readout electronics for the T2K experiment: P. Baron, X. de la Broïse, C. Coquelet, E. ...
doi:10.1109/tns.2008.2002080
fatcat:lq3fffcgyfa3beehlru5575ww4
Flexible and Reconfigurable Mismatch-Tolerant Serial Clock Distribution Networks
2012
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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Routing clock lines serially allows optimal wire usage for clock networks by eliminating the redundant wires required to match path delays. ...
We route the clock line serially, using an averaging technique to eliminate skew between clock regions in a domain. ...
ACKNOWLEDGMENT The authors would like to thank CMC Microsystems for providing access to design and manufacturing resources. ...
doi:10.1109/tvlsi.2011.2104982
fatcat:g2gfz5uwxje4xcokb6i7h4xxg4
Clock distribution networks in synchronous digital integrated circuits
2001
Proceedings of the IEEE
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The field of clock distribution network design and analysis can be grouped into a number of subtopics: 1) circuit and layout techniques for structured custom digital integrated circuits; 2) the automated ...
A theoretical background of clock skew is provided in order to better understand how clock distribution networks interact with data paths. ...
The concept of a permissible range for the clock skew of a local data path is illustrated in Fig. 19 . ...
doi:10.1109/5.929649
fatcat:eppzijpvzncvnpjzkgenkug6ni
Synchronization issues in real-time systems
1994
Proceedings of the IEEE
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of a common system-wide time base. ...
In distributed real-time systems, the mechanisms that ensure fair access to shared resources, achieve consistent deadlines, meet timing or precedence constraints, and avoid deadlocks all utilize the notion ...
AA2 Validity ]: The clock v alue of any non-faulty node is within the range of the values of all other non-faulty nodes' clocks at time t. ...
doi:10.1109/5.259425
fatcat:7mo3jwihsjhohjm3ovyjntyyj4
Time-warp correction and calibration in photonic time-stretch analog-to-digital converter
2008
Optics Letters
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dynamic range. ...
We show how time warps caused by nonuniform wavelength-to-time mapping in the photonic time-stretch analog-to-digital converter (ADC) can be digitally measured and removed. ...
Even though much of the skews can be removed in hardware by adjusting electronic clocks and delays using feedback, some residual skews remain, which effectively appear as sharp time warps at channel boundaries ...
doi:10.1364/ol.33.002674
pmid:19015705
fatcat:tn57ocge7nb6jf3ylhcsfxtx5q
A new clock network synthesizer for modern VLSI designs
2012
Integration
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Both the clock skew and the PVT (process, voltage and temperature) variations contribute a lot to the behavior of the digital circuits. ...
In this paper, a novel clock tree synthesizer is proposed for performance improvement. Several algorithms are introduced to tackle the issues accordingly. ...
The clock skew should be maintained inside prescribed latency range in order to ensure the digital function of the system. ...
doi:10.1016/j.vlsi.2011.11.001
fatcat:4heaimv54fe53jsbbn6yvcjyxq
StarSync: An extendable standard-cell mesochronous synchronizer
2014
Integration
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Variable depth buffering is provided, supporting a wide range of short and long range communications and accommodating multi-cycle wire delays. ...
It is suitable for implementation using standard cell design and requires neither delay lines nor other full custom circuits. ...
An all-digital synchronizer that exploits the predictability of periodic clocks is proposed by [21] . ...
doi:10.1016/j.vlsi.2013.09.003
fatcat:yexlhrdx6jcjhkavj4mgw26ire
Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture
2009
2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
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With the advent of Networks-on-Chip (NoCs), the interest for mesochronous synchronizers is again on the rise due to the intricacies of skew-controlled chip-wide clock tree distribution. ...
A single clock signal is distributed to the various macrocells in the design with an arbitrary amount of space-dependent time-invariant phase offset (i.e., the skew). ...
In most SoCs, the reset signal coming into the chip is an asynchronous input. Therefore, reset de-assertion should be synchronized in the receive clock domain. ...
doi:10.1109/nocs.2009.5071473
dblp:conf/nocs/LudoviciSBBG09
fatcat:ywllvvaezzc2fc4uwmbaej5b5a
PET system synchronization and timing resolution using high-speed data links
2010
2010 17th IEEE-NPSS Real Time Conference
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.; Colom Abstract-Current PET systems with fully digital trigger rely on early digitization of detector signals and the use of digital processors, usually FPGAs, for recognition of valid gamma events on ...
This is usually achieved by connecting all boards to a common backplane with a precise clock delivery network; however, this approach forces a rigid structure on the whole PET system and may pose scalability ...
ADCs and Delay Compensation ADCs with serial outputs are very useful for trigger acquisition boards because the reduced number of digital traces simplifies board layout and reduces digital signal skew ...
doi:10.1109/rtc.2010.5750335
fatcat:l3ri27yfhzhdjeawdjdclerqbu
PET System Synchronization and Timing Resolution Using High-Speed Data Links
2011
IEEE Transactions on Nuclear Science
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.; Colom Abstract-Current PET systems with fully digital trigger rely on early digitization of detector signals and the use of digital processors, usually FPGAs, for recognition of valid gamma events on ...
This is usually achieved by connecting all boards to a common backplane with a precise clock delivery network; however, this approach forces a rigid structure on the whole PET system and may pose scalability ...
ADCs and Delay Compensation ADCs with serial outputs are very useful for trigger acquisition boards because the reduced number of digital traces simplifies board layout and reduces digital signal skew ...
doi:10.1109/tns.2011.2140130
fatcat:tx6gbrxc5rhm5fqytixqaelpaq
A Background Correlation-Based Timing Skew Estimation Method for Time-Interleaved ADCs
2021
IEEE Access
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circuits or reference ADC channels. • No need to use any digital filters for the estimation process. • Wide range estimation of timing skew. • Simple structure and low hardware resources. • For convergence ...
CONCLUSION In this paper, an all-digital background calibration method for timing skew mismatch in TI-ADCs has been presented. ...
doi:10.1109/access.2021.3067355
fatcat:33urmciwufcv3i6zq72yjbxwn4
Functional Basis for Efficient Physical Layer Classical Control in Quantum Processors
2016
Physical Review Applied
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This approach leverages the simplicity of real-time Walsh-function generation in classical digital hardware, and the fact that a wide variety of physical-layer controls such as dynamic error suppression ...
Design drivers and key functionalities are introduced, leading to the selection of Walsh functions as an effective functional basis for both programming and controller hardware implementation. ...
All n Walsh Generators are triggered simultaneously (after a delay of one clock cycle), using a DFF. ...
doi:10.1103/physrevapplied.6.064009
fatcat:foaupy6ltreh5gvii3zo3ho3ay
Time Synchronization Solution for FPGA-based Distributed Network Monitoring
2018
Infocommunications journal
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Proper, system-wide time-stamping is inevitable for network monitoring and traffic analysis point of view. ...
This paper presents a closed control loop solution implemented in an FPGA-based device in order to minimize the jitter, and compensate the calculated delay. ...
Nevertheless, synchronizing all clocks within the site with nanosecond-range precision, is still a challenge. ...
doi:10.36244/icj.2018.1.1
fatcat:vlxqnoc4zbhopodm6dpyj27pne
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