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An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance
2000
IEEE Journal of Solid-State Circuits
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This paper describes an all-analog multiphase delay-locked loop (DLL) architecture that achieves both wide-range operation and low-jitter performance. ...
A replica delay line is attached to a conventional DLL to fully utilize the frequency range of the voltage-controlled delay line. ...
While a conventional analog DLL [1] uses a voltage-controlled delay line (VCDL), the wide-range analog DLL [2] uses phase mixers for wide-range operation. ...
doi:10.1109/4.826820
fatcat:whbod2cvofdznoevbge3nvmzna
A Design of 6.8 mW All Digital Delay Locked Loop with Digitally Controlled Dither Cancellation for TDC in Ranging Sensor
2020
IEEE Access
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A digital controller is proposed to detect the lock state, performs dither cancelation and selects the optimum ACC value for controlling the delay of the replica DCDL for TDC operation. ...
ADDLL uses the accumulator (ACC) to control the delay of digitally controlled delay line (DCDL) during phase locking which utilizes less power and area as compared to analog delay locked loop (DLL). ...
But it still uses VCDL and delay is controlled by an analog voltage. ...
doi:10.1109/access.2020.2982180
fatcat:c6v2qhz74jhsnkir3unhc7vy4i
A dual-loop delay-locked loop using multiple voltage-controlled delay lines
2001
IEEE Journal of Solid-State Circuits
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This paper describes a dual-loop delay-locked loop (DLL) which overcomes the problem of a limited delay range by using multiple voltage-controlled delay lines (VCDLs). ...
The DLL incorporates a replica biasing circuit for low-jitter characteristics and a duty cycle corrector immune to prevalent process mismatches. ...
He has worked on architectures and CMOS circuits for high-speed I/O interfaces. His current research interests include high-speed CMOS circuits and communication ICs. ...
doi:10.1109/4.918916
fatcat:dhbcnfmttbcxdm56z2u4plhk3i
A WideRange DelayLocked Loop with a Fixed Latency of One Clock Cycle
[chapter]
2009
Phase-Locking in High-Performance Systems
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A delay-locked loop (DLL) with wide-range operation and fixed latency of one clock cycle is proposed. ...
This DLL uses a phase selection circuit and a start-controlled circuit to enlarge the operating frequency range and eliminate harmonic locking problems. ...
Second, a solution called an all-analog DLL using a replica delay line [7] has been developed to solve the narrow frequency range problem of a conventional DLL. ...
doi:10.1109/9780470545492.ch57
fatcat:atgeejecx5g5bojgf2k2g3e3si
A 2.1-mW 0.3V-1.0V wide locking range multiphase DLL using self-estimated SAR algorithm
2009
2009 IEEE International SOC Conference (SOCC)
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This paper presents an all-digital multiphase delay-locked loop (ADMDLL) for wide-locking range and micro-power applications. ...
In addition, the FES can reuse the delay line to reduce circuit area and power dissipation significantly. ...
In this paper, a novel all-digital multiphase delay-locked loop (ADMDLL) is proposed to achieve wide-locking range, low power, and fastlock abilities. ...
doi:10.1109/soccon.2009.5398082
dblp:conf/socc/ChangCH09
fatcat:6gboh2uwwngnzfsgjbukuioumi
A 0.5–5-GHz Wide-Range Multiphase DLL With a Calibrated Charge Pump
2007
IEEE Transactions on Circuits and Systems - II - Express Briefs
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A 0.5-5 GHz wide-range multiphase delay-locked loop (MDLL) with a calibrated charge pump is presented. ...
A multiperiod-locked technique is used to enhance the input frequency range of a MDLL and avoid the harmonic-locked problem. ...
INTRODUCTION I N RECENT years, the delay-locked loop (DLL) is widely used for synchronization, clock generation [1] , [2] and digital transceivers [3] in serial links. ...
doi:10.1109/tcsii.2007.904155
fatcat:b734gthzhrb2zaotbapdwa6pqe
A Wide-Range Mixed-Mode DLL for a Combination 512 Mb 2.0 Gb/s/pin GDDR3 and 2.5 Gb/s/pin GDDR4 SDRAM
2008
IEEE Journal of Solid-State Circuits
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A mixed-mode delay-locked loop (MDLL) for a 512 Mb graphics SDRAM is presented in this paper. ...
A short discussion of some of the side effects and advantages of using a divided, multi-phase clock for logic operation is presented. ...
The on-die synchronization circuit must cover a wide operation range and, at the same time, achieve good jitter performance. ...
doi:10.1109/jssc.2007.916623
fatcat:rxr2w7um7neijp2hrpnvyu2e5u
A Highly Expandable Forwarded-Clock Receiver with Ultra-Slim Data Lane using Skew Calibration by Multi-Phase Edge Monitoring
2012
JSTS Journal of Semiconductor Technology and Science
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A source-synchronous receiver based on a delay-locked loop is presented. ...
In addition, the weightadjusted dual-interpolating delay cell, which is used in the multiphase DLL, guarantees sufficient phase linearity without using dummy delay cells, while offering a high-frequency ...
ACKNOWLEDGMENTS This work was supported by the IDEC (IC Design Education Center) and the ISRC (Inter-University Semiconductor Research Center) of Seoul National University, Seoul, Korea. ...
doi:10.5573/jsts.2012.12.4.433
fatcat:pahasjdmdjce5cqdez72jailfq
Architectures for multi-gigabit wire-linked clock and data recovery
2008
IEEE Circuits and Systems Magazine
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Acknowledgment The authors would like to thank Toshiba America Electronic Components (TAEC), Inc. for their support. ...
Also, the phase tracking loop uses a voltage-controlled delay line (VCDL) for phase synchronization instead of a VCO. ...
Many researchers have proposed a wide variety of CDR designs for high-speed wire-linked data transmission applications, such those based on an analog phase locked loop (APLL) [3] - [6] , a digital phase ...
doi:10.1109/mcas.2008.930152
fatcat:x3b6gbodvnekpewevpq6fflmzi
A Wide-Tracking Range Clock and Data Recovery Circuit
2008
IEEE Journal of Solid-State Circuits
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A split-tuned analog phase-locked loop (PLL) provides eight equally spaced phases needed for quarter-rate data recovery and the digital CDR loop adjusts the phase of the PLL output clocks in a precise ...
A hybrid analog-digital quarter-rate clock and data recovery circuit (CDR) that achieves a wide-tracking range and excellent frequency and phase tracking resolution is presented in this paper. ...
Gil-Cho Ahn, and Dr. Min Gyu Kim, and all the members of Intel Circuit Research Labs Signalling team for useful discussions and critical feedback. ...
doi:10.1109/jssc.2007.914290
fatcat:f36tl7sghvaapaepxgn4czwwtu
Clocking Analysis, Implementation and Measurement Techniques for High-Speed Data Links—A Tutorial
2009
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
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Index Terms-Clock distribution, clock recovery, high-speed I/O, phase-locked loops. ...
The performance of high-speed wireline data links depend crucially on the quality and precision of their clocking infrastructure. ...
Kennedy, and R. Mooney for collaboration and helpful discussions. ...
doi:10.1109/tcsi.2008.931647
fatcat:m2zj3kalbvad7ee5m2znin4t7u
A Phase Lookahead DTC for Fast Settling Switched Loop DPLL
[article]
2018
arXiv
pre-print
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Hence, with the proposed DTC and a proportional-integral-derivative (PID) controller based loop, we are able to achieve a low-jitter fractional-N DPLL with fastest settling time of 1us reported until now ...
In most digital-to-time converter (DTC) based applications, apart from maintaining low integral non-linearity (INL), it is also required of the system to achieve a wide frequency translation range. ...
PERFORMANCE COMPARISON While the DCDL based DTCs achieve low INL with low power consumption, this performance is achieved with the limitations of (i) low operational frequency range and (ii) time-consuming ...
arXiv:1806.03055v1
fatcat:zahaexkbkrawjlsgccxfsq47jm
A 1.2 V 0.4 mW 20~200 MHz DLL Based on Phase Detector Measuring the Delay of VCDL
2022
Electronics
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A delay locked loop (DLL) based on a Phase Detector, which Measures the Delay of the Voltage-controlled delay line (PD-MDV), which is tVCDL, with efficient and stable locking performance was proposed. ...
In the reverse case, the PD-MDV prohibits DN pulses from continuing to appear under the condition tVCDL > tREF, thereby freeing the DLL from harmonic locking and becoming stuck in the slowest operation ...
The DLL with a wide locking range as in [9] used the proper band-selection technique, requiring an additional digital-to-analog converter and many digitally controlled delay cells. ...
doi:10.3390/electronics11152434
fatcat:53qmnat3ofhabjhtier2hpzeea
A Digital Calibration Technique for Charge Pumps in Phase-Locked Systems
2008
IEEE Journal of Solid-State Circuits
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A digital technique is adopted to calibrate the current mismatch of the charge pump (CP) in phase-locked systems. In this digital calibration technique, there is no extra replica CP needed. ...
The measured output spur levels are less than 68.5 dBc throughout the whole output frequency range. The measured phase noise is 110 dBc/Hz at an offset frequency of 1 MHz. ...
ACKNOWLEDGMENT The authors would like to thank the National Chip Implementation Center for chip implementation. ...
doi:10.1109/jssc.2007.914283
fatcat:jnggcrkot5e53mhji3otrvwcgi
A serial-link transceiver based on 8-GSamples/s A/D and D/A converters in 0.25-μm CMOS
2001
IEEE Journal of Solid-State Circuits
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This paper presents a transceiver that uses a 4-bit flash analog-to-digital converter (ADC) for the receiver and an 8-bit current-steering digital-to-analog converter (DAC) for the transmitter. ...
Equalization algorithms using the converters compensate for the 1.5-GHz transceiver bandwidth to allow 8-GSamples/s multilevel data transmission. ...
Chang, A. Emami, D. Liu, and J. Wong for assistance in developing the chip. They also acknowledge National Semiconductor for fabrication. They especially thank P. ...
doi:10.1109/4.962288
fatcat:fv6e5l7loneo3njqum6pu5bujq
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