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Page 589 of Mathematical Reviews Vol. , Issue 93b
[page]
1993
Mathematical Reviews
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Summary: “A systolic algorithm is described for generating, in lexicographically ascending order, all combinations of m objects chosen from {1,---,”}. ...
Dymacek (1-WLEE)
93b:05010
93b:05006 05A05 05-04 65Y05
Stojmenovié, Ivan (3-OTTW-C)
A simple systolic algorithm for generating combinations in lexicographic order.
Comput. Math. ...
Page 1643 of Mathematical Reviews Vol. , Issue 94c
[page]
1994
Mathematical Reviews
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Summary: “A systolic algorithm is described for generating, in
lexicographically ascending order, all combinations of m objects chosen from an arbitrary set of n elements. ...
Stojmenovic¢, Ivan (3-OTTW-C; Ottawa, ON)
A simple optimal systolic algorithm for generating permutations. ...
Listing combinatorial objects in parallel
2006
International Journal of Parallel, Emergent and Distributed Systems
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This article surveys parallel generation algorithms for listing all combinatorial objects of certain type. The algorithms are designed for a very simple model, linear array of processors. ...
How to design an algorithm for generating set partitions that will satisfy Properties 1 -6 (in lexicographic or other order)? ...
It is an open problem to design parallel algorithms for listing the following cases of the restricted or generalized permutations: permutations of m out of n elements in lexicographic order, permutations ...
doi:10.1080/17445760500355777
fatcat:hyv74hfce5akdczakpibqb5adq
SYSTOLIC GENERATION OF COMBINATIONS FROM ARBITRARY ELEMENTS
1992
Parallel Processing Letters
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A systolic algorithm is described for generating, in lexicographically ascending order, all combinations of rn o$ects chosen from an arbitrary set of n elements. ...
The 'lgorithm is cost-optimal (assuming the time to output the combinations is counted), a,nd does not deal with very large integers, Kellwoxbt Combinations, linear array of processors, generating combinatorial ...
There exist algorithms for generating permutations [24] and derangements [25] satisfying criteria (1)-(6). ...
doi:10.1142/s0129626492000374
fatcat:w6gpyyxnffcibisq5ezgvb5hxq
A data locality optimizing algorithm
2004
SIGPLAN notices
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Our paper "A Data Locality Optimizing Algorithm" presented an automatic blocking algorithm for perfect loop nests on uniprocessors and multiprocessors [8] . ...
In each of my attempts to optimize data locality, first with Michael Wolf then with Amy Lim, we ended up finding an algorithm for parallelization first before solving the locality problem. ...
doi:10.1145/989393.989437
fatcat:eajlltosg5gjbhqtdituqhh3hi
FPGA Generators of Combinatorial Configurations in a Linear Array Model
2008
2008 International Symposium on Parallel and Distributed Computing
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For implementation several systolic algorithms were selected that generate combinatorial configurations in a linear array model. ...
In this paper we describe hardware implementations of generators of combinatorial objects. ...
Acknowledgements The research was supported in part by a research grant number E-7/423/BW/2008 obtained from CUT by the first author. ...
doi:10.1109/ispdc.2008.48
dblp:conf/ispdc/KokosinskiH08
fatcat:t5td5bmp3jacnj33ozzzxukwfi
A data locality optimizing algorithm
1991
SIGPLAN notices
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Our paper "A Data Locality Optimizing Algorithm" presented an automatic blocking algorithm for perfect loop nests on uniprocessors and multiprocessors [8] . ...
In each of my attempts to optimize data locality, first with Michael Wolf then with Amy Lim, we ended up finding an algorithm for parallelization first before solving the locality problem. ...
doi:10.1145/113446.113449
fatcat:2ovh6wjxmjhorne6ox3dlj47ha
On Parallel Generation of t—Ary Trees in an Associative Model
[chapter]
2002
Lecture Notes in Computer Science
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In this paper a new parallel algorithm is presented for generation of t-ary trees. Computations run in an associative processor model. ...
Tree sequences are generated in lexicographic order, with O(1) time per object, in a new representation, as combinations with repetitions with restricted growth. ...
Algorithm TREEGEN generates, in the form of t-sequences, all t-ary trees with n internal nodes in the lexicographic order with constant time per tree in an associative model with n+1 processors, each of ...
doi:10.1007/3-540-48086-2_25
fatcat:vymk6j4brzglpkjjg43dvgxrg4
Synthesizing transformations for locality enhancement of imperfectly-nested loop nests
2014
25th Anniversary International Conference on Supercomputing Anniversary Volume -
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We present an approach for synthesizing transformations to enhance locality in imperfectly-nested loops. ...
The product space is then transformed further to enhance locality, after which fully permutable loops are tiled, and code is generated. ...
Figure 11 shows an algorithm that finds a nearby legal permutation. ...
doi:10.1145/2591635.2667179
fatcat:x3uqhtqh55exzd6guuapwahiui
Synthesizing transformations for locality enhancement of imperfectly-nested loop nests
2000
Proceedings of the 14th international conference on Supercomputing - ICS '00
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We present an approach for synthesizing transformations to enhance locality in imperfectly-nested loops. ...
The product space is then transformed further to enhance locality, after which fully permutable loops are tiled, and code is generated. ...
Figure 11 shows an algorithm that finds a nearby legal permutation. ...
doi:10.1145/335231.335245
dblp:conf/ics/AhmedMP00
fatcat:kwkqtl4zujbq7izrjrrmaafpim
Dual Super-Systolic Core for Real-Time Reconstructive Algorithms of High-Resolution Radar/SAR Imaging Systems
2012
Sensors
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As an implementation test case, the proposed approach was aggregated in a HW/SW co-design scheme in order to solve the nonlinear ill-posed inverse problem of nonparametric estimation of the power spatial ...
A high-speed dual super-systolic core for reconstructive signal processing (SP) operations consists of a double parallel systolic array (SA) machine in which each processing element of the array is also ...
For the loop permutation, the following unimodular transformation 0 1 1 0 ⎡ ⎤ = ⎢ ⎥ ⎣ ⎦ P T was applied in order to permute the index-space of the locally recursive algorithm The source Polytope is described ...
doi:10.3390/s120302539
pmid:22736964
pmcid:PMC3376574
fatcat:rh3ohzgyabfvngoam3enitca6m
Page 1661 of Mathematical Reviews Vol. , Issue 91C
[page]
1991
Mathematical Reviews
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It was proved by Kolmogorov that for any set S there exists an optimal coding of S (in an appropriately defined way). ...
An interesting feature of this algorithm is that it finds a highest-level-first schedule: such a schedule defines a lexicographically first solution to this problem in a natural way. ...
Transformations for imperfectly nested loops
1996
Proceedings of the 1996 ACM/IEEE conference on Supercomputing (CDROM) - Supercomputing '96
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Our approach is an extension of the linear loop transformation framework for perfectly nested loops, and it models permutation, reversal, skewing, scaling, alignment, distribution and jamming. ...
In this paper, we present an approach to transforming imperfectly nested loops directly. ...
In this paper, we present an approach to transforming imperfectly nested loops that trades o generality for simplicity. ...
doi:10.1145/369028.369051
fatcat:i6sbfqwc3rgw5f2r5ioesei4eq
Constraint directed CAD tool for automatic latency-optimal implementation of 1-D and 2-D Fourier transforms
2002
Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications IV
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A specialized CAD tool is described that will take a user's high level code description of a non-uniform affinely indexed algorithm and automatically generate abstract latency-optimal systolic arrays. ...
The tool is then used to generate new 1-D and 2-D hardware efficient systolic arrays for the discreet Fourier transform that take advantage of the use of the radix-4 matrix decomposition. ...
In order to achieve better throughputs SPADE was used to generate more regular solutions with sub-optimal areas by setting the secondary objective function to look for maximum regularity arrays. ...
doi:10.1117/12.455338
fatcat:jcwzawy755c3nleaxxqfcwbvye
Hardware synthesis for systems of recurrence equations with multidimensional schedule
2008
International Journal of Embedded Systems
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We explain how to combine the allocation and memory functions in order to meet the computer owns rule, and we present an original mechanism for controlling the operation of the architecture. ...
This paper introduces methods for extending the classical systolic synthesis methodology to multidimensional time. ...
In any given processor, it generates an enable signal for each variable. ...
doi:10.1504/ijes.2008.022398
fatcat:frxv6j57dnduvke57hk5jnhxxa
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