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Dynamically tuning processor resources with adaptive processing

D.H. Albonesi, R. Balasubramonian, S.G. Dropsbo, S. Dwarkadas, E.G. Friedman, M.C. Huang, V. Kursun, G. Magklis, M.L. Scott, G. Semeraro, P. Bose, A. Buyuktosunoglu (+2 others)
2003 Computer  
Despite this relatively fine-grained voltage-gating approach, the DRI-cache's area and speed overhead are less than 8 percent.  ...  , network, operating system, and applications.  ... 
doi:10.1109/mc.2003.1250883 fatcat:qcwpb552pzaaflerlmyrbohndm

Runtime energy management for many-core systems

Andre L. M. Martins, Anderson C. Sant'Ana, Fernando G. Moraes
2016 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)  
This work proposes a Runtime Energy Management (REM) for many-core systems using finegrain DVFS as the primary power control policy.  ...  Due to the complexity of developing a power management solution, researchers adopt high-level models which abstract characteristics of real systems.  ...  The latency of fine-grain voltage scaling is lower than hundreds of nanoseconds [15] and allows more flexibility in controlling power.  ... 
doi:10.1109/icecs.2016.7841212 dblp:conf/icecsys/MartinsSM16 fatcat:gpvqjm2vczbvvbludafpdk2a6i

CuttleSys: Data-Driven Resource Management forInteractive Applications on Reconfigurable Multicores [article]

Neeraj Kulkarni, Gonzalo Gonzalez-Pumariega, Amulya Khurana, Christine Shoemaker, Christina Delimitrou, David Albonesi
2020 arXiv   pre-print
Core reconfiguration opens up more opportunities for colocation,as it allows the hardware to adjust to the dynamic performance and power needs of a specific mix of co-scheduled applications.  ...  We evaluate CuttleSys on multicores with tens of reconfigurable cores and show up to 2.46x and 1.55x performance improvements compared to core-level gating and oracle-like asymmetric multicores respectively  ...  fine-grained per- of resource slices when multiple applications are hosted on a formance/power tuning.  ... 
arXiv:2008.00329v1 fatcat:ixlacql2srfsldcosl6wpbldua

Towards Dynamic Voltage/Frequency Scaling for Power Reduction in Data Centers

Cong Feng Jiang, Ying Hui Zhao, Jian Wan
2010 Applied Mechanics and Materials  
In this paper, we give a short survey and discussion on some issues and aspects of DVS/DFS in data centers.  ...  Higher power consumption in data centers results in more heat dissipation, cooling costs and degrades the system reliability.  ...  Acknowledgments The funding support of this work by  ... 
doi:10.4028/ fatcat:fyw57sfzbbcqxkdxfjz4lqsm2y

Energy Efficient Computing Systems: Architectures, Abstractions and Modeling to Techniques and Standards [article]

Rajeev Muralidhar and Renata Borovica-Gajic and Rajkumar Buyya
2020 arXiv   pre-print
Computing systems have undergone several inflexion points - while Moore's law guided the semiconductor industry to cram more and more transistors and logic into the same volume, the limits of instruction-level  ...  the power intent or properties at different layers (b) modeling and simulation of the entire system or subsystem (hardware or software or both) so as to be able to perform what-if analysis, (c) techniques  ...  regulators OS guided / controlled sleep states, fine grained clock/power gating, per-core, per- module DVFS, on-die voltage regulators Memory wall, newer memory technologies Memory DVFS, compiler  ... 
arXiv:2007.09976v2 fatcat:enrfj2qgerhyteapwykxcb5pni

Variability Mitigation in Nanometer CMOS Integrated Systems: A Survey of Techniques From Circuits to Software

Abbas Rahimi, Luca Benini, Rajesh K. Gupta
2016 Proceedings of the IEEE  
| Variation in performance and power across manufactured parts and their operating conditions is an accepted reality in modern microelectronic manufacturing processes with geometries in nanometer scales  ...  We provide a comparative evaluation of methods for deployment across various layers of the system from circuits, architecture, to application software.  ...  On the other hand, coarse-grained error correction is less intrusive and often controls one of the CMOS knobs for adjusting the entire of desired block under control. 1) Fine-Grained Controllability:  ... 
doi:10.1109/jproc.2016.2518864 fatcat:sxrsu3excbdg5p7sk4iczz262y

Ctherm: An Integrated Framework for Thermal-Functional Co-simulation of Systems-on-Chip

Sumeet S. Kumar, Amir Zjajo, Rene van Leuken
2015 2015 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing  
This paper presents Ctherm, an integrated framework for cycle-accurate thermal and functional evaluation of systems-on-chip.  ...  The presented framework enables accurate characterization of thermal behaviour by generating detailed physical models for components based on input specifications, and simulating them within a tightly  ...  ACKNOWLEDGMENT This research was supported in part by the CATRENE programme under the Computing Fabric for High Performance Applications (COBRA) project CA104.  ... 
doi:10.1109/pdp.2015.56 dblp:conf/pdp/KumarZL15 fatcat:gmtwg32lhnds5j4vd5ht7awtw4

Watt Watcher: Fine-Grained Power Estimation for Emerging Workloads

Michael LeBeane, Jee Ho Ryoo, Reena Panda, Lizy Kurian John
2015 2015 27th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)  
WattWatcher operates by passing event counts and a hardware descriptor file into configurable back-end power models based on McPAT.  ...  This paper introduces WattWatcher, a multicore power measurement framework that offers fine-grained functional unit breakdowns.  ...  Any opinions, findings, conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views our sponsors.  ... 
doi:10.1109/sbac-pad.2015.26 dblp:conf/sbac-pad/LeBeaneRPJ15 fatcat:qp4e22rc3jf2znbvpxiabmncbu

Exploring Hardware Profile-Guided Green Datacenter Scheduling

Weichao Tang, Yu Wang, Haopeng Liu, Tao Zhang, Chao Li, Xiaoyao Liang
2015 2015 44th International Conference on Parallel Processing  
However, existing studies mainly focus on the temporal variability of the power supply and demand, while largely ignore the spatial variation issue in server hardware.  ...  Due to the limited, time-varying green power generation, matching server power demand to runtime power budget is often crucial in green datacenters.  ...  Fine-Grained Frequency and Voltage Control Our framework is based on the frequency and voltage control capability of existing processor microarchitecture.  ... 
doi:10.1109/icpp.2015.10 dblp:conf/icpp/TangWLZLL15 fatcat:jk7qlt5q3veb5iub6z62sxj3my

vCap: Adaptive power capping for virtualized servers

Can Hankendi, Sherief Reda, Ayse K. Coskun
2013 International Symposium on Low Power Electronics and Design (ISLPED)  
Power capping on server nodes has become an essential feature in data centers for controlling energy costs and peak power consumption.  ...  For a given set of applications, vCap first decides which applications to co-schedule based on application scalability and then optimizes the QoS in an application-aware manner for each VM by adaptively  ...  We show that scalability-based co-scheduling outperforms prior co-scheduling methods that solely consider application resource use. • We propose a fine-grained power capping technique, vCap, that is able  ... 
doi:10.1109/islped.2013.6629334 dblp:conf/islped/HankendiRC13 fatcat:usu3spwfjrg3vaukhrjrzza47y

Design Automation of Approximate Circuits With Runtime Reconfigurable Accuracy

Georgios Zervakis, Hussam Amrouch, Jorg Henkel
2020 IEEE Access  
Controlling the applied level of approximation dynamically at runtime is a key to effectively optimize energy, while still containing and bounding the induced errors at runtime.  ...  a high cost of increased dynamic power.  ...  The approximate circuits generated by RETSINA offer the user a very fine grain control of the applied approximation at runtime.  ... 
doi:10.1109/access.2020.2981395 fatcat:vrm3wicelrfx5mjzarrio3do7i

Guest Editors' Introduction: High-Performance Reconfigurable Computing

Duncan Buell, Tarek El-Ghazawi, Kris Gaj, Volodymyr Kindratenko
2007 Computer  
H igh-performance reconfigurable computers (HPRCs) 1,2 based on conventional processors and field-programmable gate arrays (FPGAs) 3 have been gaining the attention of the high-performance computing community  ...  in the past few years. 4 These synergistic systems have the potential to exploit coarse-grained functional parallelism as well as fine-grained instruction-level parallelism through direct hardware execution  ...  Only a library-based parallel tool such as the message-passing interface can handle scaling an application beyond one node in a parallel system.  ... 
doi:10.1109/mc.2007.91 fatcat:jkzmltwyp5gy5ajn4yewgz5txe

Survey on Coarse Grained Reconfigurable Architectures

Vaishali Tehre, Ravindra Kshirsagar
2012 International Journal of Computer Applications  
Novel system on chip architectures should be able to execute multiple performances demanding applications while maintaining low power consumption, small area, nonrecurring engineering costs and short time  ...  Hence a lot of research is going on to implement CGRA in SOC because Coarse-grained reconfigurable architecture can provide both performance and flexibility.  ...  can have quite different effects on the application performance depending on the characteristics of the application, which also highlights the need for memory architecture evaluation early in the design  ... 
doi:10.5120/7429-0104 fatcat:nb5kpk3ja5g2dlilbeudebl77a

An FPGA Architecture and CAD Flow Supporting Dynamically Controlled Power Gating

Assem A. M. Bsoul, Steven J. E. Wilton, Kuen Hung Tsoi, Wayne Luk
2016 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Finally, we study a control system of a robot that is used in endoscopy. Using the proposed architecture combined with clock gating results in up to 19% energy savings in this application.  ...  In this paper, we present an FPGA architecture that enables dynamically controlled power gating, in which FPGA resources can be selectively powered down at run-time.  ...  Furthermore, enhancements to the CAD tools are required in order to better guide the different stages in the flow to increase idle times and increase the number of resources that can be powered down, while  ... 
doi:10.1109/tvlsi.2015.2393914 fatcat:hg67damqgvdc3onknpftjxhnqe

Challenges and Opportunities in Many-Core Computing

J.L. Manferdelli, N.K. Govindaraju, C. Crall
2008 Proceedings of the IEEE  
operating system schedulers.  ...  ABSTRACT | In this paper, we present some of the challenges and opportunities in software development based on the current hardware trends and the impact of massive parallelism on both the software and  ...  Within a process, the application and supporting runtime in conjunction with the OS can exert very fine grain control over resources.  ... 
doi:10.1109/jproc.2008.917730 fatcat:nh32zeed2fbvph2xcoan7ejjsm
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