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An iterative algorithm for partitioning and scheduling of area constrained HW-SW systems
Proceedings Tenth IEEE International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype (Cat. No.PR00246)
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This paper presents a technique for integrated p artitioning and scheduling of hardware-software systems. ...
We use an iterative approach where the partitioner assigns the mapping of only some of the tasks and the remaining tasks are assigned by the scheduler with an objective of minimizing the execution time ...
Conclusion We presented a new algorithm for partitioning and scheduling of area constrained HW-SW systems. ...
doi:10.1109/iwrsp.1999.779043
dblp:conf/rsp/ChathaV99
fatcat:siuki5qmhvfynb6xhgi5et7z3a
Hardware-software partitioning and pipelined scheduling of transformative applications
2002
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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The tool uses iterative partitioning and pipelined scheduling to obtain optimal partitions that satisfy the timing and area constraints. ...
We present techniques for generation of good initial solution and search-space limitation for the branch and bound algorithm. A candidate partition is evaluated by generating its pipelined schedule. ...
The for the partitioned task graph is then given by maximum of and , that is . 2) Pipelined HW-SW Implementation: The tool for partitioning and pipelined scheduling of HW-SW systems is shown in Fig. 4 ...
doi:10.1109/tvlsi.2002.1043323
fatcat:5piedlpp6vgv3jvfhdjkl7cbfi
A path analysis based partitioning for time constrained embedded systems
1998
Proceedings of the sixth international workshop on Hardware/software codesign - CODES/CASHE '98
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The HW/SW partitioning problem addressed in this paper is one of the key steps in the co-design flow of heterogeneous embedded systems. ...
Therefore, we introduce an heuristic for synthesizing heterogeneous systems that uses a global metric to guide the mapping of tasks according to the reusability of components and the time margin induced ...
In this solution,
88 ---
Concluding remarks and future works Our algorithm performs the HW/SW partitioning and the scheduling of a time constrained static task graph specification and constructs a ...
doi:10.1145/278241.278307
dblp:conf/codes/BiancoAGP98
fatcat:a3tnzdxncbdopckeduecgsbg5i
Particle Swarm Optimization for HW/SW Partitioning
[chapter]
2009
Particle Swarm Optimization
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Finding an optimal HW/SW partition is hard because of the large number of possible solutions for a given granularity of the "components" and the many different alternatives for these granularities. ...
The HW/SW partitioning problem is, thus, an optimization problem where we seek to find the partition ( an assignment vector of each component to HW or SW) that minimizes a user-defined global cost function ...
In short, delay and area costs needed for the HW/SW partitioning task are only known accurately post the scheduling task. Obviously, this situation calls for time-wasteful iterations. ...
doi:10.5772/6740
fatcat:74m2cqgijnggrhjnide3n3pq2e
HW/SW codesign techniques for dynamically reconfigurable architectures
2002
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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approach to reconfigurable computing multicontext scheduling; and 3) a HW/SW partitioning algorithm for dynamically reconfigurable architectures. ...
Index Terms-Dynamic scheduling, dynamically reconfigurable architectures, HW/SW codesign, HW/SW partitioning. 1063-8210/02$17.00 © 2002 IEEE Juanjo Noguera received the B.. ...
ACKNOWLEDGMENT The authors acknowledge the Department of Research and Development of Hewlett-Packard Inkjet Commercial Division, Barcelona, Spain, for its support in the preparation of his Ph.D. dissertation ...
doi:10.1109/tvlsi.2002.801575
fatcat:3ojhhmr27fgxzcuvvj2xwbmyf4
Hardware/software partitioning and pipelined scheduling on runtime reconfigurable FPGAs
2010
ACM Transactions on Design Automation of Electronic Systems
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Given an application in the form of a task graph with known execution times on the HW (FPGA) and SW (CPU), and known area sizes on the FPGA, find an valid allocation of tasks to either HW or SW and a static ...
We address two problems related to HW task scheduling on PRTR FPGAs: (1) HW/SW partitioning. ...
-HW/SW Partitioning and Scheduling on a Hybrid FPGA/CPU Device. ...
doi:10.1145/1698759.1698763
fatcat:xnur36bxt5hhja2uh7v5hjqnaq
Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration
2005
Proceedings of the 42nd annual conference on Design automation - DAC '05
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We propose an exact and a heuristic formulation that simultaneously partition, schedule, and do linear placement of tasks on such architectures. ...
We present a physically aware hardware-software (HW-SW) scheme for minimizing application execution time under HW resource constraints, where the HW is a reconfigurable architecture with partial dynamic ...
In this work, we consider the problem of task level HW-SW partitioning for a resource-constrained system, where the HW device has partial RTR capability. ...
doi:10.1145/1065579.1065667
dblp:conf/dac/BanerjeeBD05
fatcat:vuj6elaqjfhrzmimg24cjq4yya
A Modified Binary Firefly Algorithm to Solve Hardware/Software Partitioning Problem
2021
Informatica (Ljubljana, Tiskana izd.)
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Hardware/Software (Hw/Sw) partitioning is a crucial step in Hw/Sw co-design that determines which components of the embedded system could be implemented on hardware and which ones on software. ...
The main purpose of this paper is to present a modified binary firefly algorithm to solve Hw/Sw partitioning problems. ...
, for the financial support of Embedded System Laboratory (LASE). ...
doi:10.31449/inf.v45i7.3408
fatcat:pzbaivbddrajpgttdttuvr5azu
A codesign experiment in acoustic echo cancellation: GMDFα
1997
ACM Transactions on Design Automation of Electronic Systems
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HW/SW codesign approaches consist generally of HW/SW partitioning and scheduling, constrained code generation, and hardware and interface synthesis. ...
This article presents the codesign of an industrial experiment in acoustic echo cancellation (GMDF␣ algorithm) and emphasizes the partitioning and communication synthesis steps. ...
Commonly, codesign comprises several tasks, including system specification, HW/SW partitioning and scheduling, constrained code generation, communication synthesis, and HW/SW integration. ...
doi:10.1145/268424.268433
fatcat:otlapxx5sjbtzirxmwvd5hurfm
Integrating Physical Constraints in HW-SW Partitioning for Architectures With Partial Dynamic Reconfiguration
2006
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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We first present an exact approach for hardware-software (HW-SW) partitioning that guarantees correctness of implementation by considering placement implications as an integral aspect of HW-SW partitioning ...
Next, we present a physically aware HW-SW partitioning heuristic that simultaneously partitions, schedules, and does linear placement of tasks on such devices. ...
ACKNOWLEDGMENT The authors would like to thank the anonymous reviewers for their helpful comments that significantly improved the clarity of their paper. ...
doi:10.1109/tvlsi.2006.886411
fatcat:jjwx65abcnbmddeksuov7fwn5m
Hardware/Software Partitioning and Static Task Scheduling on Runtime Reconfigurable FPGAs using a SMT Solver
2008
2008 IEEE Real-Time and Embedded Technology and Applications Symposium
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In this paper, we formulate and solve the problem of optimal hardware/software partitioning and static task scheduling for a hybrid FPGA/CPU device, with the optimization objective of minimizing the total ...
A runtime reconfigurable FPGA allows part of the FPGA area to be reconfigured while the remainder continues to operate without interruption, so that hardware tasks can be placed and removed dynamically ...
We have implemented the heuristic algorithm for HW-SW partitioning in [12] , which is based on the well-know KLFM (Kernighan-Lin/Fiduccia-Matheyses) heuristic that iteratively improves a HW/SW partitioning ...
doi:10.1109/rtas.2008.39
dblp:conf/rtas/YuanHG08
fatcat:tyzjgol3szhvjhuy6molkmex7i
Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration
2005
Proceedings. 42nd Design Automation Conference, 2005.
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We propose an exact and a heuristic formulation that simultaneously partition, schedule, and do linear placement of tasks on such architectures. ...
We present a physically aware hardware-software (HW-SW) scheme for minimizing application execution time under HW resource constraints, where the HW is a reconfigurable architecture with partial dynamic ...
In this work, we consider the problem of task level HW-SW partitioning for a resource-constrained system, where the HW device has partial RTR capability. ...
doi:10.1109/dac.2005.193828
fatcat:hqgzewiyxzh6nf45msj63sp64e
A software-hardware cosynthesis approach to digital system simulation
1994
IEEE Micro
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The components of the simulation compiler are a high performance compiled-code software simulator, an automatic partitioner that partitions the system model between the processor and FPGA, and a scheduler ...
We describe these components and show how they can be used to improve the performance of synchronous digital system simulation by up to a factor of two when compared to a high performance all software ...
Acknowledgments We would like to thank the reviewers for their insightful comments on earlier drafts of this paper. This research was supported by a grant from the Powell Foundation. ...
doi:10.1109/40.296157
fatcat:xnex5qaserfsxigjvh2vyjguue
Hardware/Software Partitioning Algorithm Based on Genetic Algorithm
2014
Journal of Computers
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To solve the hardware/software(HW/SW) partitioning problem on the system that contains only one CPU, a new algorithm based on GA is studied. ...
Firstly, the concept of hardware orientation is put forward, and then used to create the initial colony of GA and in mutation process, which reduces the randomicity of initial colony and the blindness ...
Paper [12] partitioned the system into hardware and software components using GA where an enhanced resource constrained scheduling algorithm was used to determine system performance, as a result, execution ...
doi:10.4304/jcp.9.6.1309-1315
fatcat:ujq2jge4h5cqbo3lshiayedsce
Pipelined Scheduling of Functional HW/SW Modules for Platform-Based SoC Design
2005
ETRI Journal
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We developed a pipelined scheduling technique of functional hardware and software modules for platformbased system-on-a-chip (SoC) designs. It is based on a modified list scheduling algorithm. ...
We used the pipelined scheduling technique for a performance analysis of an MPEG4 video encoder application. Then, we applied it for architecture exploration to achieve a better performance. ...
HW-SW co-design consists of two basic design stages: partitioning the application specification into HW and SW components, and scheduling the execution order of these components. ...
doi:10.4218/etrij.05.0905.0011
fatcat:5vuh2zd2rzejpmiaak3qjd3qdi
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