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Page 154 of International Journal of Optical Computing Vol. 1, Issue 2 [page]

1990 International Journal of Optical Computing  
Section 2 provides an introduction to systolic arrays (SA) in view of an application to optical computing.  ...  Section 4 describes the SA used to implement this division algorithm and in Section 5 the mapping of the SA to an optical architecture which processes data planes by SSL is described in detail.  ... 

High Performance Systolic Architecture by Evolutionary Design

Hanumanthareddy P S
2014 IOSR Journal of VLSI and Signal processing  
Using EP, we are able to find the number of different solutions for designing the systolic architecture for regular iterative algorithms.  ...  This paper focuses on design of systolic architecture and by the application of evolutionary programming to achieve 100% HUE (Hardware Utilization Efficiency) for space representation containing delays  ...  Systolic design methodology maps an N-dimensional DG to a lower dimensional systolic architecture. Mapping of N-dimensional DG to (N-1) dimensional systolic array is considered.  ... 
doi:10.9790/4200-04420611 fatcat:eufvdm6j25ccdgre6c3efyg6am

Design and FPGA Implementation of Systolic Array Architecture for Matrix Multiplication

Mahendra Vucha, Arvind Rajawat
2011 International Journal of Computer Applications  
This paper demonstrates an effective design for the Matrix Multiplication using Systolic Architecture on Reconfigurable Systems (RS) like Field Programmable Gate Arrays (FPGAs).  ...  Here, the RTL code is written for matrix multiplication with systolic architecture and matrix multiplication without systolic architecture in Verilog HDL, compiled and simulated by using Modelsim XE III  ...  INTRODUCTION In computer architecture, a systolic architecture is a pipelined network arrangement of Processing Elements (PEs) called cells.  ... 
doi:10.5120/3084-4222 fatcat:ge36plsjtbb3xo2da6amzt6i4i

General-purpose systolic arrays

K.T. Johnson, A.R. Hurson, B. Shirazi
1993 Computer  
Second, desktop computers distribute processing power to the user in an easily customized open architecture.  ...  With advances in VLSI, WSI, and FPGA technologies, they have progressed from fixedfunction to generalpurpose architectures. hen Sun Microsystems introduced its first workstation, the company could not  ...  "systolicizing" them provides an efficient way t o ensure fault tolerance: any fault tolerance precautions built into one cell are extensible to all cells. computational performance.  ... 
doi:10.1109/2.241423 fatcat:5pbdb7wypbbqzk7riagtv5jsvq

Low Power Systolic Array Based Digital Filter for DSP Applications

S. Karthick, S. Valarmathy, E. Prabhu
2015 The Scientific World Journal  
The proposed systolic array filter has reduced leakage power up to 8.5% than the existing filter architectures.  ...  Systolic array based digital filter used in signal processing of electrocardiogram analysis is presented with datapath architectural innovations in low power consumption perspective.  ...  Other than the distributed arithmetic, the design specific systolic array architectures were also utilized to build the filter architecture.  ... 
doi:10.1155/2015/592537 pmid:25922854 pmcid:PMC4398960 fatcat:gs2hkopwtncqdo2iuj5lar3z74

On the Difficulty of Designing Processor Arrays for Deep Neural Networks [article]

Kevin Stehle and Günther Schindler and Holger Fröning
2020 arXiv   pre-print
We present an analysis of popular DNN models to illustrate how it can estimate required cycles, data movement costs, as well as systolic array utilization, and show how the progress in network architecture  ...  show a huge diversity in operations due to a large design space: An operand's dimension varies substantially since it depends on design principles such as receptive field size, number of features, striding  ...  A major breakthrough in neural architectures is the introduction of advanced connectivity between layers which leads to significant improvements in parameter and computation efficiency.  ... 
arXiv:2006.14008v1 fatcat:3cy43d2cwjdsvk36wwix5daxuu

Design and Implementation of Adaptive FIR filter using Systolic Architecture

Ravi H Bailmare, S.J. Honale, Pravin V Kinge
2014 International Journal of Reconfigurable and Embedded Systems (IJRES)  
Systolic architecture is an arrangement of processor where data flows synchronously across array element.  ...  In order to obtain minimum mean square error and updated value of weight vector effectively, systolic architecture is used.  ...  Low adaption delay architecture for implementation of DLMS adaptive filter is achieved by using an efficient implementation of systolic architecture.  ... 
doi:10.11591/ijres.v3.i2.pp54-61 fatcat:za4bfpl7xnatbfhjqpfqdfrsha

DHT algorithm based on encoding algebraic integers

R. Baghaie, V. Dimitrov
1999 Electronics Letters  
Furthermore, for the implementation of the algorithm a fully pipelined systolic architecture with O(N) throughput is proposed.  ...  With the aid of this scheme, an error-free representation of the cas function becomes possible.  ...  Since the introduction of the DHT, a number of systolic architectures have been proposed, many of which are based on the direct implementation of algorithm [3, 4] .  ... 
doi:10.1049/el:19990947 fatcat:p7rx5nxafbao5n4vrxqeo7wpom

Design of IIR Systolic Array Architecture by using Linear Mapping Technique

Manoj Kumar
2019 International Journal of Computer Applications  
Systolic array architecture maps high level computations into hardware structures. In a systolic array, all the processing elements (PEs) are uniform and fully pipelined.  ...  Various IIR systolic arrays architectures such as design B1, design B2, and design F is proposed in this paper.  ...  Linear mapping technique maps an Ndimensional dependence graph to a lower dimensional systolic architecture.  ... 
doi:10.5120/ijca2019918463 fatcat:2h2mlvkf4jak7gauo5yqgys44u

Performance Analysis of Fixed Point FIR Filter Architectures

P R Sreesh, L S Kumar
2020 2020 Third International Conference on Advances in Electronics, Computers and Communications (ICAECC)  
Different FIR filter architectures such as the conventional method, systolic architecture, associativity transformation and combination of systolic and associativity transformation architectures are considerd  ...  This paper compares different types of fixed point FIR filter architectures and analyze the different perfomance parameters such as area, hardware utlization and delay.  ...  The systolic architecture comprises several processing elements (PEs) that calculate and transfer data.We can get an array that combines two adjacent PE arrays to one.  ... 
doi:10.1109/icaecc50550.2020.9339519 fatcat:m7br7ivxcvdcxo6t5iwfc6goee

Design and Implementation of FIR Filter Architecture Using High Level Transformation Techniques

V. Jamuna, P. Gomathi, A. Arun
2018 Indian Journal of Science and Technology  
Findings: The FIR filter is designed with 4-Tap, 8-Tap and 16-Tap length and the designed architecture using Systolic architecture with Associativity technique shows 8.9%, 2.3% and 2.4% reduction in LUT  ...  Objectives: FIR filter structure is designed with area and delay optimization is designed using Systolic Architecture and Associativity High Level Transformation technique in this paper.  ...  The function of an FIR filter is to accept the input signal and blocking specific frequency and passing the real signal minus those components to the output side.  ... 
doi:10.17485/ijst/2018/v11i17/122769 fatcat:vvz3i77jjrec7pvq4o77ox2ipq

Designing a Novel Reversible Systolic Array Using QCA

Mohammad Mahdi Abdollahi, Mohammad Tehrani
2017 Italian Journal of Science & Engineering  
This article has been proposed a novel architecture for QCA circuits in order to utilizing in complicated control systems based on systolic arrays with high throughput and least power dissipation. 1-Introduction  ...  FET-based Devices since the 1970s has been created and nowadays FETs have an incredible improvement however, FETs got serious effects making any progress in scaling more difficult because of 0.1 um limitations  ...  The Majority gate (figure 1C) can be operated as an OR gate or an AND gate by getting a constant input to one of the inputs.  ... 
doi:10.28991/ijse-01118 fatcat:l5yax3z6jzhunhsrfq2ftlw7gm

Design of Systolic Architecture Using Evolutionary Computation

Shilpa V, Suma V Shetty
2018 International Journal of Trend in Scientific Research and Development  
This Approach also having the focus to minimize the total delay involved with systolic architecture design. Evolutionary programming has applied to find the optimal solution.  ...  The Proposed method having capability to find the large number of optimal vectors for any algorithm which can be implemented in systolic architecture.  ...  INTRODUCTION The essential goal of developing new computer architectures and efficient use of existing modern systems is to run larger and more complicated applications faster over time.  ... 
doi:10.31142/ijtsrd15776 fatcat:526gpna2hndt3kaec37pgkh2fu

A Novel Design of Low Power, High Speed SAMM and its FPGA Implementation

Anuja George
2012 International Journal of Computer Applications  
This work demonstrates an effective design and efficient implementation of the Matrix Multiplication using Systolic Architecture and Ancient mathematics.  ...  The work also includes the comparison between three design approaches of the matrix multiplication using systolic architecture. In the first design approach, array multipliers were used.  ...  Systolic Architecture A systolic architecture is an array of Processing Elements, each called as a cell. Each cell is connected to a small number of nearest neighbours in a mesh like topology.  ... 
doi:10.5120/6089-8263 fatcat:ak3pozllwre3ha5cjktoiiaaza

Embedded Parallel Systolic architecture for multi-filtering techniques using FPGA

Muataz H. Salih, M. R. Arshad
2010 2010 2nd International Conference on Electronic Computer Technology  
Keywords-embedded system design; FPGA system design; systolic architecture; underwater detection I.  ...  To enhance the performance of these systems by increasing the processing power, a new architecture and clocking technique is carried out in this paper.  ...  ACKNOWLEDGMENT The authors would like to thank the Underwater Robotics Research Group (URRG) in USM for their assistance and MOSTI for providing the research grant (grant no. 605124).  ... 
doi:10.1109/icectech.2010.5479973 fatcat:ibvimtetszaa3bn7hiwnk34e7a
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