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An Improved Unified Scalable Radix-2 Montgomery Multiplier
17th IEEE Symposium on Computer Arithmetic (ARITH'05)
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This paper describes an improved version of the Tenca-Koç unified scalable radix-2 Montgomery multiplier with half the latency for small and moderate precision o perands and half the queue memory requirement ...
An FPGA implementation can perform 1024-bit modular exponentiation in 16 ms using 5598 4-input lookup tables, making it the fastest unified scalable design yet reported. ...
Conclusion This paper has described an improvement on the Tenca-Koç unified scalable radix-2 Montgomery multiplier. ...
doi:10.1109/arith.2005.9
dblp:conf/arith/HarrisKAMH05
fatcat:chdg6kqv65bfja4hizvfheywt4
Parallelized radix-4 scalable montgomery multipliers
2007
Proceedings of the 20th annual conference on Integrated circuits and systems design - SBCCI '07
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This paper describes a parallelized radix-4 scalable Montgomery multiplier implementation. ...
This is comparable to radix-2 for long multiplies and nearly twice as fast for short ones. ...
Parallelized Radix-4 Scalable Design The parallelized radix-4 scalable algorithm is a hybrid of two previous Montgomery multiplier designs: the improved unified scalable radix-2 design [3] and the parallelized ...
doi:10.1145/1284480.1284562
dblp:conf/sbcci/PinckneyH07
fatcat:wbjirxbcfjazjbxjl6ve66t3xq
Very high radix scalable Montgomery multipliers
2005
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)
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This paper describes a very high radix scalable Montgomery multiplier. It extends the radix-2 Tenca-Koç scalable architecture using w × v -bit integer multipliers in place of AND gates. ...
The new design can perform 1024-bit modular exponentiation in 6.6 ms using 2847 4-input lookup tables and 32 16 x 16 multipliers, making it the fastest scalable design yet reported. ...
This paper presents a very high radix scalable Montgomery multiplier. It extends the scalable architecture of [9] to radix 2 v by using a w × v-bit multiplier. ...
doi:10.1109/iwsoc.2005.111
dblp:conf/iwsoc/KelleyH05
fatcat:2msngs2k7jdjrnzzk6ndhe354e
Design and implementation of scalable low power radix-4 Montgomery modular multiplier
2007
2007 International Conference on Computer Engineering & Systems
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This paper proposes an efficient algorithm and Processing Element (PE) architecture for a Multiple Word Radix 4 Montgomery Modular (MWR4MM) multiplier. ...
scalability. ...
In [12] a scalable radix 2 modular multiplier is presented. ...
doi:10.1109/icces.2007.4447076
fatcat:llfoycepgbcjfok4ld5pij4kge
Page 440 of IEEE Transactions on Computers Vol. 52, Issue 4
[page]
2003
IEEE Transactions on Computers
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In [8], a unified scalable Montgomery Multiplier design is presented. ...
The work in [7] intro- duces a scalable and unified multiplier. ...
A versatile Montgomery multiplier architecture with characteristic three support
2009
Computers & electrical engineering
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We present a novel unified core design which is extended to realize Montgomery multiplication in the fields GF(2 n ), GF(3 m ), and GF(p). ...
The metric shows that the new unified architecture provides an improvement over a hypothetical non-unified architecture of at least 24.88%, while the improvement over a classical unified architecture is ...
Radix-3 Montgomery multiplication algorithm for GF(3 m ) Montgomery multiplication algorithms for GF(p) and GF(2 n ) are similar to each other because they are both implemented in radix-2. ...
doi:10.1016/j.compeleceng.2008.05.009
fatcat:ir3ortkunngnpavfhupepdtbb4
Time Efficient Dual-Field Unit for Cryptography-Related Processing
[chapter]
2010
IFIP Advances in Information and Communication Technology
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In this paper we propose a novel unified architecture for parallel Montgomery multiplication supporting both GF (N ) and GF (2 n ) finite field operations, which are critical for RSA ad ECC public key ...
Furthermore, it relies on a modified Booth recoding scheme for the multiplicand and a radix-4 scheme for the modulus, enabling reduced time delays even for moderately large operand widths. ...
For GF (2 n ) operations, elements are
Fig. 3 . 3 An example of radix-4 Montgomery multiplication execution
Fig. 4 . 4 The basic row in the proposed radix-4 parallel Montgomery multiplier
Fig. 5 ...
doi:10.1007/978-3-642-12267-5_11
fatcat:47kgsgd2ina5tbfoowq474lw6m
Page 1221 of IEEE Transactions on Computers Vol. 52, Issue 9
[page]
2003
IEEE Transactions on Computers
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Koc, “A Scalable and Unified Multiplier
eds Ppp
Incomplete Reduction in Modular 149, no. 2
Architecture for Finite Fields GF(p) and GF(2 Proc. ...
Boston: Kluwer
70-77
vol
Architecture for Montgomery Hardware and 94-108,
Todorov, and C.K. Koc, “High-Radix Design of a Scalable Modular Multiplier,” Proc. ...
Efficient Unified Arithmetic for Hardware Cryptography
[chapter]
2009
Cryptographic Engineering
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of the Montgomery multiplication algorithm for binary extension fields, GF (2 n ) given in [8] . ...
Quite contrarily, a unified module that is capable of performing arithmetic in more than one field in the same, unified datapath brings about many advantages, one of which is the improved {area × time} ...
Dual-Radix Multiplier The original unified multiplier in [12] uses radix-2 design and offers an equal performance for both GF (p) and GF (2 n ) of the same precision in terms of clock count. ...
doi:10.1007/978-0-387-71817-0_6
fatcat:ghtbkwpi45fala6m73j2e5xsie
Finite Field Arithmetic for Cryptography
2010
IEEE Circuits and Systems Magazine
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Dual-Radix Multiplier The original unified multiplier in [47] uses radix-2 design and offers an equal performance for both GF1p 2 and GF12 n 2 of the same precision in terms of clock count. ...
Implementations of unified multiplier in ASIC standard cell library demonstrate that unified multiplier significantly improves area x time metric. ...
doi:10.1109/mcas.2010.936785
fatcat:y6ya7xmjk5doznqj5lxxrnodoe
Achieving NTRU with montgomery multiplication
2003
IEEE transactions on computers
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In this paper, we propose a new unified architecture that utilizes the Montgomery Multiplication algorithm to perform a modular multiplication for both integers and binary polynomials and NTRU's polynomial ...
The unified design is capable of supporting a majority of public-key cryptosystems such as NTRU, RSA, Diffie-Hellman key exchange, and Elliptic Curve schemes, among others. ...
ACKNOWLEDGMENTS The authors thank Gunnar Gaubatz for his contributions to the unified Montgomery Multiplier core design. ...
doi:10.1109/tc.2003.1190585
fatcat:kuybatdgfbg3jjfr6hndvaiwma
Design of a scalable RSA and ECC crypto-processor
2003
Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC
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In this paper, we propose a scalable word-based crypto-processor that performs modular multiplication based on modified Montgomery algorithm for finite fields GF´Pµ and GF´2 m µ. ...
The unified crypto-processor supports scalable keys of length up to 2048 bits for RSA and 512 bits for elliptic curve cryptography (ECC). ...
Fig. 1 . 1 The word-based radix-2 Montgomery multiplication algorithms over (a) GF´Pµ and (b) GF´2 m µ. ...
doi:10.1145/1119772.1119874
dblp:conf/aspdac/SunSHW03
fatcat:jmyvt5tbg5a3ni44jlhtbzcaaa
Multifunction Residue Architectures for Cryptography
2014
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
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An analysis of input/output conversions to/from residue representation, along with the proposed residue Montgomery multiplication algorithm, reveals common multiply-accumulate data paths both between the ...
a dual-field residue arithmetic Montgomery multiplier are presented in this paper. ...
Their performance has been improved by high-radix algorithms and architectures [26] - [28] . ...
doi:10.1109/tcsi.2013.2283674
fatcat:qvr6hohdl5hpjet5ouhyzrwd2y
Hardware architectures for public key cryptography
2003
Integration
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The "ideally designed" hardware should offer a scalable architecture to overcome the well-known drawback of limited flexibility. ...
Commonly used finite fields in ECC protocols are GF (p) and GF (2 n ). The basic operation for RSA is multiplication in GF (p). ...
The basic observation to provide the unified Montgomery multiplier is that an adder module, equipped with the property of performing addition with or without carry, is available. ...
doi:10.1016/s0167-9260(02)00053-6
fatcat:u5pkdeitprh77hcaaui66nzv24
Design of Cryptographic Hardware Architecture for Mobile Computing
2009
Journal of Information Processing Systems
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The proposed cryptographic hardware has a chip area of 38K gates for RSA and 12.4K gates for unified SHA-1 and SHA-256 respectively on a 0.25um CMOS process. ...
Therefore, we can apply n double CSA modules to the multiplier core to implement the radix-2 n modular multiplication. ...
The multiplier core block is the functional block implementing the proposed Montgomery algorithm summarized in Algorithm 2. ...
doi:10.3745/jips.2009.5.4.187
fatcat:g2ika2m5o5gcrkoyg6vhax2iqy
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