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An improved decimal redundancy check

Roger L. Sisson
1958 Communications of the ACM  
Let the final product in the range be mx, so that: AN IMPROVED DECIMAL REDUNDANCY CHECK RoGER L. SISSON, Canning, Sisson & Associates, Los Angeles, Calif.  ...  An example is given of how this fact may be used to improve the checking.  ... 
doi:10.1145/368819.368854 fatcat:5ccmwmqyebedfadw2hukuz5ssu

Page 10 of Communications of the Association for Computing Machinery Vol. 1, Issue 5 [page]

1958 Communications of the Association for Computing Machinery  
AN IMPROVED DECIMAL REDUNDANCY CHECK RoGER L. SISSON, Canning, Sisson & Associates, Los Angeles, Calif.  ...  An example is given of how this fact may be used to improve the checking.  ... 

Modified decimal matrix codes for error detection in memory using pipeline architecture

Anagha. K.N, Raghu. M.C.
2016 International Journal of Advanced Research  
However the number of redundant bits required was elevated. To reduce this Decimal Matrix codes were designed. The basic error correcting codes comprises of an encoder and a decoder units.  ...  These codes employs the simple decimal operations such as addition, XOR operation etc for the check bit generation. This scheme of error correction is explained with an example of a 32 bit data.  ... 
doi:10.21474/ijar01/1038 fatcat:ys2zoii3xvhevllyv7i3fjuov4

A High Performance Decimal Matrix Code Architecture for Improved Reliable Memory
english

M. SATYA SRI, K.JYO THI
2014 International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering  
Therefore, in this paper, we present a high performance Decimal Matrix Code to assure the reliability of memory.  ...  This protection code utilizes decimal procedure to detect errors, so that more errors were detected and corrected up to 32.  ...  H 0 -H 39 are horizontal check bits; V 0 through V 31 are vertical check bits.  ... 
doi:10.15662/ijareeie.2014.0310043 fatcat:76qwhsr4tzh5zatqll3ufdabjy

FPGA Implementation of Low Power High Speed BTED Algorithm for 8 Bit Error Correction in Cryptography System

Ramesha M
2020 International Journal of Emerging Trends in Engineering Research  
The simulation results shows that there is 18% improvement in delay, 15% in power reduction and 67% improvement in hardware resources utilizations compared to conventional algorithms.  ...  Figure.2 depicts encoder module having 32-bit input and producing an output of 20-bit horizontal redundant number and 16-bit vertical redundant number.  ...  As shown in Equation ( 1 ) to (8) by decimal addition in horizontal redundant bits 'H' are obtained.  ... 
doi:10.30534/ijeter/2020/158872020 fatcat:753ifoazhzelpleumqanag44sa

A fully redundant decimal adder and its application in parallel decimal multipliers

Saeid Gorgin, Ghassem Jaberipur
2009 Microelectronics Journal  
In the proposed fully redundant adder (VS semi-redundant ones such as decimal carry-save adders) both operands and sum are redundant decimal numbers with overloaded decimal digit set [0, 15] .  ...  Two alternative architectures for decimal multipliers are presented; one is slower, but area-improved, and the other one consumes more area, but is delay-improved.  ...  a very fast fully redundant decimal addition scheme, based on an unsigned redundant decimal digit set and show its efficient application in parallel decimal multiplication.  ... 
doi:10.1016/j.mejo.2009.07.002 fatcat:vkr32gj44ffepfaiettr7pmyj4

Implementation of Sha-3 for Security and Error Detection and Correction Mechanism to Enhance Memory Reliabilty

Asha T R, Hamsaveni N
2015 International Journal of Engineering Research and  
In this paper, novel decimal matrix code (DMC) is used to improve the memory reliability. DMC is based on divide-symbol and it utilizes decimal algorithm to maximize error detection capability.  ...  The secure hash algorithm (SHA)-3 that is keccak is selected in 2012 to provide security to any application that requires hashing, pseudo-random number generation, and integrity checking.  ...  H0-H19 are horizontal check or redundancy bits; V0 through V15 are vertical redundancy bits.  ... 
doi:10.17577/ijertv4is050753 fatcat:qg64ls7ez5a4zg4zg6n66om6ve

Generalized Information Security and Fault Tolerant based on Redundant Residue Number System

Idris Abiodun, Kazeem Alagbe
2017 International Journal of Computer Applications  
Information Security is an extensive issue and covers a huge number of crimes.  ...  In this paper, a generalized information security and fault tolerant system using Redundant Residue Number System (RRNS) was proposed, the theoretical result show that our proposed scheme is out performed  ...  Redundancy is added to the information/data, therefore the code rate decreases and error correction property is improved.  ... 
doi:10.5120/ijca2017914563 fatcat:rph6ntqwrjcqvpoc6p3c2o4v2e

FPGA implementation of RGB image encryption and decryption using DNA cryptography

Fazal Noorbasha, K Suresh
2018 International Journal of Engineering & Technology  
Two-bit error detection and correction for each pixel of the image can be performed.DNA code improves security and use of the Hamming code for error detection and correction.  ...  Simulation Results An error has occurred can be checked during transmission by using check bits for hamming code, If check bit value is zero then received data has no error.  ...  Single bit error correction can be implemented using both check and parity bits, sometimes an error occurs in parity bit position also it cannot be detected by check bits but it can be detected by using  ... 
doi:10.14419/ijet.v7i2.8.10469 fatcat:l4bllzznhjelbmmjg6g6nicffq

VLSI ARCHITECTURE FOR ERROR DETECTION AND CORRECTION BASED ON XOR AGAINST MULTIPLE CELL UPSETS WITH REDUCED REDUNDANT BITS

V. Bhanumathi, M. Sunandini
2019 ICTACT Journal on Microelectronics  
It is understood from the simulation analysis that the proposed architecture achieves low area, power, and delay with an improved capability of error correction and detection.  ...  more redundant bits for detection.  ...  The limitation of DMC is shown in Fig.6 with an example. In DMC, horizontal redundant bits are calculated for both original and MCU bits. Based on that decimal difference the MCU bits are detected.  ... 
doi:10.21917/ijme.2019.0131 doaj:ad73f05cdb264bfda959e53350a8624d fatcat:2sv2u3vitrawvaod6plttpba3m

Lookup Table Algorithm for Error Correction in Color Images

Ruaa Alaadeen Abdulsattar, Nada Hussein M. Ali
2018 JOIV: International Journal on Informatics Visualization  
A color image of type BMP is considered as an application of developed lookup table algorithms to detect and correct errors in these images.  ...  Decimal Matrix Code (DMC) and Hamming code (HC) techniques were integrated to compose Hybrid Matrix Code (HMC) to maximize the error detection and correction.  ...  The channel encoding procedure involves adding redundancy in the form of parity check-bits and encoding-decoding logic circuits to improve data robustness to noise during transmission.  ... 
doi:10.30630/joiv.2.2.113 fatcat:4tvory5rqfds3jzl4jzhygg4qy

Improving the speed of decimal division

A. Kaivani, A. Hosseiny, G. Jaberipur
2011 IET Computers & Digital Techniques  
The authors study previous major contributions to digit recurrence decimal division hardware and focus on techniques for improving the performance of quotient digit selection (QDS) as the most complex  ...  Furthermore, they remove the rounding cycle by cost-free auto-rounding, which is an exclusive advantage of the digit set [25, 5] .  ...  Aiming at an area-optimised design, they keep the partial remainders in non-redundant format with 5-2-1-1 encoding of decimal digits.  ... 
doi:10.1049/iet-cdt.2010.0026 fatcat:3zi3srl7k5cpnikhivjpe4j3aa

Fully redundant decimal addition and subtraction using stored-unibit encoding

Amir Kaivani, Ghassem Jaberipur
2010 Integration  
In this paper we offer a new redundant decimal digit set [À8, 9] and a fully redundant addition/subtraction scheme.  ...  For example, the traditional fully redundant (i.e., the result and both of the operands are represented in a redundant format) and semi-redundant (i.e., the result and only one of the operands are redundant  ...  The BCD to DSD conversion is a zero-time operation, an impressive improvement over the 9DG latency of the similar conversion in [26] .  ... 
doi:10.1016/j.vlsi.2009.04.001 fatcat:tfdrjvyxojh2xiuj3u3mnte22u

Energy and Delay Improvement via Decimal Floating Point Units

Hossam A. H. Fahmy, Ramy Raafat, Amira M. Abdel-Majeed, Rodina Samy, Tarek ElDeeb, Yasmin Farouk
2009 2009 19th IEEE Symposium on Computer Arithmetic  
Interest in decimal arithmetic increased considerably in recent years.  ...  It stresses the importance of energy savings achieved by hardware implementations of the IEEE standard for decimal floating point.  ...  This scheme may produce an incorrect result in some cases. Our algorithm truncates the quotient to p digits and checks the actual remainder to decide on the correct rounding.  ... 
doi:10.1109/arith.2009.21 dblp:conf/arith/FahmyRASEF09 fatcat:6klu3s6kgbbuxcbfw73q2tkthm

An HARQ Based Optimized Error Correction Technique

Kaustuv Kunal, R. C. Tripathi, Vrijendra Singh
2010 International Journal of Computer Applications  
Row and column encoding method are dissimilar with an objective to achieve maximum correction capability with minimum redundancy.  ...  Difference is subtraction value of decimal conversion of check bits to number of ones in data bits of respective row.  ... 
doi:10.5120/1353-1826 fatcat:wyf2kqh2iree7bjb7wwn2zzlru
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