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An improved algorithm for the automatic verification of finite state systems using temporal logic
2018
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In section 3, we describe the structure of the finite state systems that we will verify. In section 4, we give an outline of our algorithm. ...
Every atomic proposition
The Finite State System Description The finite state systems that our algorithm deals with are 5-tuples, M = (S, /, O, R, P) where • S is a finite set of states. • / is a finite ...
Furthermore, the previous lemma also gives an algorithm for negating EX f that takes 0(|R|) time, so EG f is still the worst case in the proof of theorem 5. ...
doi:10.1184/r1/6603317.v1
fatcat:jyxi2kaoorhcbhyatod6yrap2m
Page 5384 of Mathematical Reviews Vol. , Issue 94i
[page]
1994
Mathematical Reviews
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The Internet Archive has digitized a microfilm copy of this work. It may be possible to borrow a copy for reading.
94i:68186
ders to improve automatic verification methods (extended abstract) (176-185).
Susanne Graf and Bernhard Steffen, Compositional minimiza- tion of finite state systems (186-196); A. ...
Yannakakis, Mem- ory efficient algorithms for the verification of temporal properties (233-242); Wuxu Peng and S. ...
On The Integration of Decision Diagrams in High Order Logic Based Theorem Provers:a Survey
2007
Journal of Computer Science
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The paper also tries to answer which is the best decision graphs formalization for theorem provers as what is the optimized set of operations to efficiently manipulate the decision graphs inside theorem ...
The approaches can be divided in two kinds, one is based on building a translation between model checker and theorem prover, the second is based on embedding the model checker algorithms inside the theorem ...
Thus, the verification of properties for finite-state systems is decidable. Much of this work is based on Binary Decision Diagrams [2] . ...
doi:10.3844/jcssp.2007.810.817
fatcat:gu5y5qe4azbpblxoebifj6ys5a
Automatic property generation for formal verification applied to HDL-based design of an on-board computer for space applications
2013
2013 14th Latin American Test Workshop - LATW
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This work presents a new method for automatic property generation for formal verification of Hardware Description Language (HDL) based systems. ...
Formal verification using model checking represents a system as formal model that are automatically generated by synthesis tools. ...
The authors would like to thank also the Cadence Academic Network (CAN) for the tools licenses. ...
doi:10.1109/latw.2013.6562663
dblp:conf/latw/SilvaBWL13
fatcat:tnqsu36s4jeorhulhom72ypgta
Recent Challenges and Ideas in Temporal Synthesis
[chapter]
2012
Lecture Notes in Computer Science
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This paper introduces the synthesis problem, algorithms for solving it, and recent promising ideas in making temporal-synthesis useful in practice. ...
While modelchecking theory has led to industrial development and use of formal-verification tools, the integration of synthesis in the industry is slow. ...
An approach in which quantitative reasoning is used in order to improve the quality of automatically synthesized systems is described in [7] . ...
doi:10.1007/978-3-642-27660-6_8
fatcat:dphuat2tk5ds3bd637h3xibxmq
Trends and Challenges in Algorithmic Software Verification
[chapter]
2008
Lecture Notes in Computer Science
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Recent years have witnessed remarkable progress in principles and tools for automated software verification. ...
In this position paper, I briefly discuss the relevant projects in my group, and outline some near-term challenges for the community as concrete milestones for measuring progress. ...
Recently, we have introduced a temporal logic of calls and returns (CaRet) for specification and algorithmic verification of correctness requirements of structured programs. ...
doi:10.1007/978-3-540-69149-5_26
fatcat:eig3aaqlhrf7pi5gqxx2kd62py
POSTER: Sechduler
2013
Proceedings of the 2013 ACM SIGSAC conference on Computer & communications security - CCS '13
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Additionally, if not both of the requirements can be satisfied simultaneously, Sechduler makes use of easy-to-define linear temporal logic-based policies as well as automatically generated Büchi automaton-based ...
Our experimental results show that Sechduler can adaptively enforce the system-wide logic-based temporal policies within the kernel and with minimal performance overhead of 3% on average to guarantee high ...
Acknowledgments The authors would like to thank the Office of Naval Research (Grant N000141210462) for their support. ...
doi:10.1145/2508859.2512527
dblp:conf/ccs/HaghaniZ13
fatcat:gfwblkotizevjgwmi7jymyrtqe
Model Checking: Historical Perspective and Example (Extended Abstract)
[chapter]
1998
Lecture Notes in Computer Science
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Model checking is an automatic verification technique for finite state concurrent systems such as sequential circuit designs and communication protocols. ...
Specifications are expressed in propositional temporal logic. An exhaustive search of the global state transition graph or system model is used to determine if the specification is true or not. ...
It is based on a language for describing hierarchical finite-state concurrent systems. Programs in the language can be annotated by specifications expressed in temporal logic. ...
doi:10.1007/3-540-69778-0_3
fatcat:flyys7zuefhpzou562dwv7hufa
Sechduler: A Security-Aware Kernel Scheduler
2013
2013 IEEE 19th Pacific Rim International Symposium on Dependable Computing
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Additionally, if not both of the requirements can be satisfied simultaneously, Sechduler makes use of easy-to-define linear temporal logic-based policies as well as automatically generated Büchi automatonbased ...
tasks in an optimal order such that, if feasible, neither realtime nor security requirements of the system are violated. ...
Sechduler then converts the policy to an extended finite state machine-based monitor automatically. ...
doi:10.1109/prdc.2013.45
dblp:conf/prdc/ZonouzHH13
fatcat:3zr2ndskmzbvths7schioduxkm
TACAS 2003 Special Issue—Preface
2006
Theoretical Computer Science
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Predicate abstraction has emerged to be a powerful automatic abstraction technique for extracting finite-state models from infinite-state systems. ...
Given a hybrid system with linear dynamics and a set of linear predicates, a verifier using predicate abstraction performs an on-the-fly search of the finite discrete quotient whose states correspond to ...
Conclusion We would like to thank heartily the referees for their expertise and their commitment to the quality of the present special issue. ...
doi:10.1016/j.tcs.2005.11.014
fatcat:wayjlqolubgvpkwhidau222pha
Progress on the State Explosion Problem in Model Checking
[chapter]
2001
Lecture Notes in Computer Science
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Model checking is an automatic verification technique for finite state concurrent systems. ...
In this approach to verification, temporal logic specifications are checked by an exhaustive search of the state space of the concurrent system. ...
Finally, the logics used for specifications can directly express many of the properties that are needed for reasoning about concurrent systems. ...
doi:10.1007/3-540-44577-3_12
fatcat:jyu7lsi2hbgqvioflllvfjulmq
A semantics driven temporal verification system
[chapter]
1988
Lecture Notes in Computer Science
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We present an overview of SMG, a generic state machine generator, which interfaces to various temporal logic model checkers and provides a practical generic temporal verification system. ...
SMG transforms programs written in user-definable languages to suitable finite state models, thus enabling fast verification of temporal properties of the input program. ...
Verification System Architecture We agree with the conclusions of [BC86,BCDM84,CES86] that the use of model checkers provides an attractive and tractable approach to automatic verification of temporal ...
doi:10.1007/3-540-19027-9_2
fatcat:okuk3f5cnzamtf7out7kqp25li
PEP — more than a Petri Net tool
[chapter]
1996
Lecture Notes in Computer Science
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The programming component allows the user to design concurrent algorithms in an easy-to-use imperative language, and the PEP system then generates Petri nets from such programs. ...
This includes user-defined properties specified by temporal logic formulae as well as specific properties for which dedicated algorithms are available. ...
Further, the following objects are used in the PEP system: 2. During verification it may become necessary to calculate the finite prefix of a branching process [8] of an existing LL net. ...
doi:10.1007/3-540-61042-1_58
fatcat:6xleev2hqjebjfv47l6sc4rnhm
Verify Your Runs
[chapter]
2008
Lecture Notes in Computer Science
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An example illustrating the use of state machines for monitoring is the TLChart system [22] , that monitors a combination of temporal logic and state machines. ...
In [28] is described an algorithm for synthesizing finite trace monitoring algorithms from LTL specifications, inspired by similar algorithms used for synthesizing infinite trace Omega automata from ...
doi:10.1007/978-3-540-69149-5_40
fatcat:pfznp4n7lng4nfczz74bwafjue
Methodology and system for practical formal verification of reactive hardware
[chapter]
1994
Lecture Notes in Computer Science
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This system was used in the verification of eight designs. ...
The realization involved the development of a system consisting of several tools, while using the SMV [McM93] verification tool as the system core. ...
Acknowledgements We thank the designers of the Haifa Design Group, whose cooperation contributed to the maturity of both the methodology and the system. ...
doi:10.1007/3-540-58179-0_53
fatcat:x6eal3hlmff25kt7a4hakua2uq
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