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An implicit method for hazard-free two-level logic minimization

M. Theobald, S.M. Nowick
Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems  
None of the available minimizers for exact 2-level hazard-free logic minimization can synthesize very large circuits.  ...  This paper introduces a new implicit 2-level logic minimizer, Impymin, which is able to solve very large multi-output hazard-free minimization problems exactly.  ...  The authors would also like t o thank Bob Fuhrer for providing his tool Hfmin, a n d Montek Singh for interesting discussions.  ... 
doi:10.1109/async.1998.666494 dblp:conf/async/TheobaldN98 fatcat:4vg5jx5z25cpndrx4je4fjlb5e

Fast heuristic and exact algorithms for two-level hazard-free logic minimization

M. Theobald, S.M. Nowick
1998 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
This paper introduces two new 2-level logic minimizers: Espresso-HF, a heuristic method which is loosely based on Espresso-II, and Impymin, an exact method based on implicit data structures.  ...  None of the available minimizers for 2-level hazard-free l o gic minimization can synthesize very large circuits.  ...  Conclusions We have presented two new minimization methods for multi-output 2-level hazard-free logic minimization: Espresso-HF, a heuristic method based on Espresso-II, and Impymin, an exact method based  ... 
doi:10.1109/43.736186 fatcat:trbwsjkrijhzpareblxpf3i6qu

Hazard analysis for safety-critical systems using SOFL

Azma binti Abdullah, Shaoying Liu
2013 2013 IEEE Symposium on Computational Intelligence for Engineering Solutions (CIES)  
A case study based on an Auto-cruise Control (ACC) system for vehicles is used as an example to illustrate the process.  ...  The most important mechanism for improving the safety of a system is to identify the hazard state of the system as it has the potential to cause an unexpected, unplanned or undesired event or a series  ...  For this function, there are two safety properties and two hazards.  ... 
doi:10.1109/cies.2013.6611740 dblp:conf/cies/AbdullahL13 fatcat:vax4npgg6nhihlmmplaaackguy

Asynchronous interface specification, analysis and synthesis

Michael Kishinevsky, Jordi Cortadella, Alex Kondratyev
1998 Proceedings of the 35th annual conference on Design automation conference - DAC '98  
The goal of this tutorial is to ll this gap and to present an overview of one popular systematic design methodology for design of asynchronous interface c ontrollers.  ...  Interfaces, by nature, are often asynchronous since they serve for connecting multiple distributed modules agents without common clock.  ...  Acknowledgments We wish to thank Luciano Lavagno, Alexander Taubin, and Alex Yakovlev for numerous discussions on the topics presented in this paper.  ... 
doi:10.1145/277044.277046 dblp:conf/dac/KishinevskyCK98 fatcat:thob4jeobfe35nhhioivemfkve

Synthesis of initializable asynchronous circuits

S.T. Chakradhar, S. Banerjee, R.K. Roy, D.K. Pradhan
1996 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
We present a novel implicit enumeration procedure that selectively assigns don't cares to obtain an initializable implementation.  ...  unknown starting state will be completely ineffective for these circuits.  ...  Chu for several useful discussions and S. Rothweiler for his help in implementationrelated issues.  ... 
doi:10.1109/92.502197 fatcat:gw2pnxjyqrfhtia5a3jpjxporm

Automatic synthesis of 3D asynchronous state machines

Yun, Dill
1992 IEEE/ACM International Conference on Computer-Aided Design  
We present an algorithm for constructing a three-dimensional next-state table, a heuristic for encoding states, and a procedure for generating necessary constraints for exact logic minimization.  ...  We estimate the latency (input to output delay) and the cycle time (time required for the circuit to stabilize after the excitation) for all benchmark designs using a 0.8pm CMOS standard cell library.  ...  Acknowledgement The authors would like to thank Steve Nowick of Stanford University for generously providing the logic minimizer and many helpful discussions.  ... 
doi:10.1109/iccad.1992.279310 dblp:conf/iccad/YunD92 fatcat:jwziitluzzhldd263g4y36ssmm

Power minimization in IC design: principles and applications

Massoud Pedram
1996 ACM Transactions on Design Automation of Electronic Systems  
This article presents an in-depth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems and describes the many issues facing designers at architectural, logical  ...  , and physical levels of design abstraction.  ...  Iman and Pedram [1995a] propose an alternative power-saving factor which assumes that nodes in the multi-level network are in two-level logic form.  ... 
doi:10.1145/225871.225877 fatcat:jv72d4vvgfcmhmsmfazpkooyge

The pricing of bank payments services

Leigh Drake, David T. Llewellyn
1995 International Journal of Bank Marketing  
Such interest-free accounts represent a cost to the consumer; they represent an implicit payment to the bank for services provided.  ...  This is one of the hazards of implicit charging: effective costs to the consumer and revenue to the bank vary with the level of interest rates, whereas the costs of supplying current account services are  ... 
doi:10.1108/02652329510147319 fatcat:6533pumkvzb63cvan4vopmqjva

Signal transition graph constraints for synthesis of hazard-free asynchronous circuits with unbounded-gate delays

Radhakrishna Nagalla, Graham Hellestrand
1994 Formal methods in system design  
A synthesis procedure for asynchronous control circuits from a high level speci cation, signal transition graph (STG), is described.  ...  In this paper, we propose some syntactic constraints on STG to guarantee hazard-free implementation.  ...  Acknowledgement The authors would like to thank Ruchir Puri for providing us with his unpublished manuscript and for many useful discussions.  ... 
doi:10.1007/bf01383833 fatcat:mj4ns2y6cna5vhdart6phjflq4

An efficient delay test generation system for combinational logic circuits

Eun Sei Park, M. Ray Mercer
1990 Conference proceedings on 27th ACM/IEEE design automation conference - DAC '90  
Xl), an unspecified logic value (XX), and two additional faulty logic values R and F.  ...  More accurate analysis of hazard signals may be possible by using either an exact timing simulation or an approximate method [8], [12] .  ... 
doi:10.1145/123186.123390 dblp:conf/dac/ParkM90 fatcat:swhac2nlpbflnpwfm2hna7mzei

An efficient delay test generation system for combinational logic circuits

Eun Sei Park, M.R. Mercer
1992 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Xl), an unspecified logic value (XX), and two additional faulty logic values R and F.  ...  More accurate analysis of hazard signals may be possible by using either an exact timing simulation or an approximate method [8], [12] .  ... 
doi:10.1109/43.144857 fatcat:uf5sntpsxfhe5nntug23vcvcpa

Formalism in Safety Cases [chapter]

John Rushby
2009 Making Systems Safer  
I am grateful to Robin Bloomfield and his colleagues at Adelard and City University for exposing me to some of these topics and sharing their own ongoing investigations.  ...  An important choice for this enterprise is the logical system in which to formalize safety case arguments.  ...  For example, we may have evidence for software based on testing and on its integrity level, and we will wish to combine these two "legs" to yield a "multi-legged" case, perhaps using BBNs [17] .  ... 
doi:10.1007/978-1-84996-086-1_1 dblp:conf/scss/Rushby10 fatcat:jfoy2mgktnenbhdtxuksuztbbe

Risk Analysis and Management for Marine Systems

Bilal M. Ayyub, Jeffrey E. Beach, Shahram Sarkani, Ibrahim A. Assakkaf
2002 Naval engineers journal (Print)  
Methods are provided in the paper that can be used to develop risk-based standards for system safety. The relationship between risk and standards is studied from a historical perspective.  ...  Great successes in controlling risk to health and safety are exemplified by the development of design methods for buildings, bridges, or super tankers that render them capable of withstanding extreme storms  ...  Several methods generate a set of minimal cut sets. One method is based on a top-down search of the Boolean logic.  ... 
doi:10.1111/j.1559-3584.2002.tb00130.x fatcat:wvu4qcjfobczle3wdrkcjl5pwa

State encoding of large asynchronous controllers

Josep Carmona, Jordi Cortadella
2006 Proceedings of the 43rd annual conference on Design automation - DAC '06  
This new method opens the door to incorporate logic synthesis in the design flow of large control circuits obtained from high-level specifications.  ...  A novel method to solve the state encoding problem in Signal Transition Graphs is presented.  ...  Acknowledgment The authors would like to thank Jose Manuel Colom for his suggestions and helpful discussions.  ... 
doi:10.1145/1146909.1147148 dblp:conf/dac/CarmonaC06 fatcat:qd4ndfmomfewlbgxspxatpxpxy

State encoding of large asynchronous controllers

J. Carmona, J. Cortadella
2006 Proceedings - Design Automation Conference  
This new method opens the door to incorporate logic synthesis in the design flow of large control circuits obtained from high-level specifications.  ...  A novel method to solve the state encoding problem in Signal Transition Graphs is presented.  ...  Acknowledgment The authors would like to thank Jose Manuel Colom for his suggestions and helpful discussions.  ... 
doi:10.1109/dac.2006.229414 fatcat:hhgdo3cl2zgdtgfbkagxajd7f4
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