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Consistency in Non-Transactional Distributed Storage Systems [article]

Paolo Viotti, Marko Vukolić
2016 arXiv   pre-print
As such, our paper complements the existing surveys done in the context of transactional, database consistency semantics.  ...  The scope of this paper is restricted to non-transactional semantics, i.e., those that apply to single storage object operations.  ...  This research was supported in part by the EU projects CloudSpaces (FP7-317555) and SUPERCLOUD (Horizon 2020 programme, grant No. 643964).  ... 
arXiv:1512.00168v4 fatcat:nv7qzsrkmje6dpbxhztrmso2iu

The semantics of x86-CC multiprocessor machine code

Susmit Sarkar, Peter Sewell, Francesco Zappa Nardelli, Scott Owens, Tom Ridge, Thomas Braibant, Magnus O. Myreen, Jade Alglave
2008 Proceedings of the 36th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages - POPL '09  
We test the semantics against actual processors and the vendor litmus-test examples, and give an equivalent abstract-machine characterisation of our axiomatic memory model.  ...  Multiprocessors are now dominant, but real multiprocessors do not provide the sequentially consistent memory that is assumed by most work on semantics and verification.  ...  We acknowledge the support of a Royal Society University Research Fellowship (Sewell), EPSRC grants GR/T11715, EP/C510712, and EP/F036345, and ANR grant ANR-06-SETI-010-02.  ... 
doi:10.1145/1480881.1480929 dblp:conf/popl/SarkarSNORBMA09 fatcat:fvm7nzborrbm7bbxd3dvsh4xmu

The semantics of x86-CC multiprocessor machine code

Susmit Sarkar, Peter Sewell, Francesco Zappa Nardelli, Scott Owens, Tom Ridge, Thomas Braibant, Magnus O. Myreen, Jade Alglave
2009 SIGPLAN notices  
We test the semantics against actual processors and the vendor litmus-test examples, and give an equivalent abstract-machine characterisation of our axiomatic memory model.  ...  Multiprocessors are now dominant, but real multiprocessors do not provide the sequentially consistent memory that is assumed by most work on semantics and verification.  ...  We acknowledge the support of a Royal Society University Research Fellowship (Sewell), EPSRC grants GR/T11715, EP/C510712, and EP/F036345, and ANR grant ANR-06-SETI-010-02.  ... 
doi:10.1145/1594834.1480929 fatcat:tkxvfndvvzg6djwt5yek7roruq

Foundations of the C++ concurrency memory model

Hans-J. Boehm, Sarita V. Adve
2008 Proceedings of the 2008 ACM SIGPLAN conference on Programming language design and implementation - PLDI '08  
We describe an effort, currently nearing completion, to address these issues by explicitly providing semantics for threads in the next revision of the C++ standard.  ...  There are no benign C++ data races. • We use weaker semantics for trylock than existing languages or libraries, allowing us to promise sequential consistency with an intuitive race definition, even for  ...  Lawrence Crowl is also responsible for most of the detailed design of the atomics interface. The anonymous reviewers provided a number of useful suggestions.  ... 
doi:10.1145/1375581.1375591 dblp:conf/pldi/BoehmA08 fatcat:b6rqjwpzmjcdvdzaqjoeyl5kfy

Foundations of the C++ concurrency memory model

Hans-J. Boehm, Sarita V. Adve
2008 SIGPLAN notices  
We describe an effort, currently nearing completion, to address these issues by explicitly providing semantics for threads in the next revision of the C++ standard.  ...  There are no benign C++ data races. • We use weaker semantics for trylock than existing languages or libraries, allowing us to promise sequential consistency with an intuitive race definition, even for  ...  Lawrence Crowl is also responsible for most of the detailed design of the atomics interface. The anonymous reviewers provided a number of useful suggestions.  ... 
doi:10.1145/1379022.1375591 fatcat:afs6fjtubzgnpphd7jquowt7xu

The semantics of power and ARM multiprocessor machine code

Jade Alglave, Anthony Fox, Samin Ishtiaq, Magnus O. Myreen, Susmit Sarkar, Peter Sewell, Francesco Zappa Nardelli
2008 Proceedings of the 4th workshop on Declarative aspects of multicore programming - DAMP '09  
We develop a rigorous semantics for Power and ARM multiprocessor programs, including their relaxed memory model and the behaviour of reasonable fragments of their instruction sets.  ...  The semantics is mechanised in the HOL proof assistant.  ...  We acknowledge the support of EPSRC grants GR/T11715, EP/C510712, and EP/F036345, and ANR grant ANR-06-SETI-010-02.  ... 
doi:10.1145/1481839.1481842 dblp:conf/popl/AlglaveFIMSSN09 fatcat:h4dlhsfd4zcbfkuggpyfrj7nkm

Mechanized Theory of Event Structures: A Case of Parallel Register Machine

Vladimir Gladstein, Dmitrii Mikhailovskii, Evgenii Moiseenko, Anton Trunov
2021 Proceedings of the Institute for System Programming of RAS  
The true concurrency models, and in particular event structures, have been introduced in the 1980s as an alternative to operational interleaving semantics of concurrency, and nowadays they are regaining  ...  Event structures represent the causal dependency and conflict between the individual atomic actions of the system directly.  ...  This encoding allows us to decouple the semantics of the register machine from a memory model. 148 an instruction pointer and a map from registers to their values , as shown in fig. 5 .  ... 
doi:10.15514/ispras-2021-33(3)-11 fatcat:l26vlarbcjdura5xtmxwpvkfwe

Application-Aware Consistency: An Application to Social Network [article]

Lewis Tseng, Alec Benzer, Nitin H. Vaidya
2015 arXiv   pre-print
The weakened models not only respect application semantic, but also yield a performance benefit.  ...  We introduce a notion of dependency graphs, which specify relations between events that are important with respect to application semantic, and then weaken traditional consistency models (e.g., causal  ...  In particular, we discuss how to use two different kinds of dependency graphs to weaken causal consistency, and why such relaxed models yield performance benefit while still being useful for social network  ... 
arXiv:1502.04395v2 fatcat:il7sfeje7fdxjgbh3ohwutbueu

On abstraction and compositionality for weak-memory linearisability [chapter]

Brijesh Dongol, Radha Jagadeesan, James Riely, Alasdair Armstrong
2017 Lecture Notes in Computer Science  
For both variants, we prove abstraction (so that programmers can reason about a client program using the sequential specification of an object rather than its more complex concurrent implementation) and  ...  This assumption is inadequate in the presence of relaxed memory models, where happens-before relations are also of importance.  ...  To reason about such implementations, we must also enrich the semantics of implementations to relate method invocation/response events with memory events.  ... 
doi:10.1007/978-3-319-73721-8_9 fatcat:jeephnn3i5emtmtvikebndowza

Semantics, Specification, and Bounded Verification of Concurrent Libraries in Replicated Systems [chapter]

Kartik Nagar, Prasita Mukherjee, Suresh Jagannathan
2020 Lecture Notes in Computer Science  
We use our framework to analyze the behavior of a number of highly non-trivial library implementations of stacks, queues, and exchangers.  ...  criteria such as linearizability that has a useful interpretation in a shared-memory context to a distributed one where the cost of imposing a (logical) global ordering on all actions is prohibitive.  ...  We thank the anonymous reviewers for their insightful comments. This material is based upon work supported by the National Science Foundation under Grant No. CCF-SHF 1717741.  ... 
doi:10.1007/978-3-030-53288-8_13 fatcat:3wx2jru3wvaynhdsufpy7gl5my

Understanding the limitations of causally and totally ordered communication

David R. Cheriton, Dale Skeen
1993 Proceedings of the fourteenth ACM symposium on Operating systems principles - SOSP '93  
Causally and totally ordered communication support  ...  Even the weakest of these semantic ordering constraints, causal memory, can not be enfomd through the use of causal muhicast [1] .  ...  Firstly, as pointed out in Section 3, the causal relationships implemented by CNOCS in a real-time system may be incomplete because many tie or semantic causal relationships a "implemented" in the monitored  ... 
doi:10.1145/168619.168623 dblp:conf/sosp/CheritonS93 fatcat:obqrakdk2fdjxekde52bqafs5e

Understanding the limitations of causally and totally ordered communication

David R. Cheriton, Dale Skeen
1993 ACM SIGOPS Operating Systems Review  
Causally and totally ordered communication support  ...  Even the weakest of these semantic ordering constraints, causal memory, can not be enfomd through the use of causal muhicast [1] .  ...  Firstly, as pointed out in Section 3, the causal relationships implemented by CNOCS in a real-time system may be incomplete because many tie or semantic causal relationships a "implemented" in the monitored  ... 
doi:10.1145/173668.168623 fatcat:3cesoqj4z5dzjlo7stkis3i6ve

A Better x86 Memory Model: x86-TSO [chapter]

Scott Owens, Susmit Sarkar, Peter Sewell
2009 Lecture Notes in Computer Science  
We give two equivalent definitions of x86-TSO: an intuitive operational model based on local write buffers, and an axiomatic total store ordering model, similar to that of the SPARCv8.  ...  Real multiprocessors do not provide the sequentially consistent memory that is assumed by most work on semantics and verification.  ...  The first issue is, again, how to interpret "causality" as used in P5.  ... 
doi:10.1007/978-3-642-03359-9_27 fatcat:hchqhp3qevagvowvnxjp2mcj5i

Ultrametric Semantics of Reactive Programs

Neelakantan R. Krishnaswami, Nick Benton
2011 2011 IEEE 26th Annual Symposium on Logic in Computer Science  
is correct with respect to the high-level semantics.  ...  We describe a denotational model of higher-order functional reactive programming using ultrametric spaces and nonexpansive maps, which provide a natural Cartesian closed generalization of causal stream  ...  Since we can implement and prove correct an implementation of each combinator used in the denotational semantics in Figure 2 By reading all of the cells with writers, we ensure that the state is complete  ... 
doi:10.1109/lics.2011.38 dblp:conf/lics/KrishnaswamiB11 fatcat:33ttn7khfrdrnnibwbsyckmmtu

Mixed consistency

Divyakant Agrawal, Manhoi Choy, Hong Va Leong, Ambuj K. Singh
1994 Proceedings of the thirteenth annual ACM symposium on Principles of distributed computing - PODC '94  
This model combines two kinds of weak memory consistency conditions: causal memory and pipelined random access memory, and provides four kinds of explicit synchronization operations: read locks, write  ...  The resulting suite of memory and synchronization operations can be tailored to solve most programming problems in an efficient manner.  ...  The implementa- tion of write operations is similar to the implementation of causal memory [4].  ... 
doi:10.1145/197917.197967 dblp:conf/podc/AgrawalCLS94 fatcat:frergg5objdj3jmgw7qy7vgh5m
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