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An Implementation Technique of Multi-Cycled Arithmetic Functions For a Dynamically Reconfigurable Processor
2006
2006 International Conference on Field Programmable Logic and Applications
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Awashima of NEC;Prof. Amano of Keio University, NEC Corp., and NEC Electronics Corp. for technical advises. ...
DRP OVERVIEW NEC's DRP is a coarse-grained multi-context dynamically reconfigurable processor architecture [1] . The structure of prototype chip DRP-l is shown in Fig. 1 . ...
INTRODUCTION Recently, technologies of coarse-grained dynamically reconfigurable processors such as Dynamically Reconfigurable Processor (DRP) by NEC Electronics have been rapidly developed [1, 2, 3, 4 ...
doi:10.1109/fpl.2006.311291
dblp:conf/fpl/MiyataTSO06
fatcat:kmbcioiq2fglliieky2kz2au2e
A Processor With Dynamically Reconfigurable Circuit For Floating-Point Arithmetic
2010
Zenodo
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Dynamic reconfiguration is a technique to realize required functions by changing hardware construction during operation. ...
This paper describes about dynamic reconfiguration to miniaturize arithmetic circuits in general-purpose processor. ...
The future work is a design of dynamically reconfigurable VLIW processor. Fig. 1 1 Dynamic reconfiguration of arithmetic circuit III. ...
doi:10.5281/zenodo.1080514
fatcat:cnjbir5rtrfmpn7tbrmb2qfrcq
Recon.gurable Computing and Digital Signal Processing
[chapter]
2001
Signal Processing and Communications
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This paper presents a survey of academic research and commercial development in reconfigurable computing for DSP systems over the past fifteen years. ...
While application-specific integrated circuits (ASICs) and programmable digital signal processors (PDSPs) remain the implementation mechanisms of choice for many DSP applications, increasingly new system ...
In conclusion, reconfiguration is a promising technique for the implementation of future DSP systems. ...
doi:10.1201/9780203908068.ch4
fatcat:d6gyesol3bc4rfwc7r4g5wf2ri
Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques
[chapter]
2005
Lecture Notes in Computer Science
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This work gives an overview of several relevant reconfigurable architectures and design techniques developed by the authors in different projects and emphasizes the effective role of reconfigurability ...
Reconfiguration emerged as a key concept to cope with constraints regarding performance, power consumption, design time and costs posed by the growing diversity of application domains. ...
System-level reconfiguration can be understood as the reconfiguration of the implemented functionality of one or multiple SoC IP cores (FPGAs, processors). ...
doi:10.1007/11512622_3
fatcat:5q4aerbfezbgdl37s72jwr6o34
An Elastic Architecture Adaptable to Various Application Scenarios
2014
Journal of Computer Science and Technology
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The elasticity of our prototype implementation of EA, as Sim-EA, ranges from 3.31 to 14.34, with 5.41 in arithmetic average, for SPEC CPU2000 benchmark suites, which provides great flexibility to fulfill ...
Moreover, Sim-EA can reduce the EDP (energy-delay product) for 31.14% in arithmetic average compared with a baseline fixed architecture. ...
For instance, the performance elasticity of a modern processor with dynamic voltage/frequency scaling (DVFS) with the frequency ranging from 1GHz to 2GHz is 2 for all applications. ...
doi:10.1007/s11390-014-1425-x
fatcat:33bxsylubzczvjy5az6guid7le
Cover and Frontmatter
2008
2008 International Conference on Application-Specific Systems, Architectures and Processors
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a Cooperative MIMO Receiver for Reconfigurable Architectures ......................................................................... 167 • A Dynamic Holographic Reconfiguration on a Four-Context ODRGA ...
91 Interactive Session 2 ............................................................................. 138 • An Efficient Implementation Of A Phase Unwrapping Kernel On Reconfigurable Hardware ....... ...
doi:10.1109/asap.2008.4580202
fatcat:ylw2sim6gnb2hbh3qjnkbcepwu
A Survey of Reconfigurable Architectures
2014
International Journal of Computer Applications
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Reconfigurable block in these architectures provides the required flexibility for a large variety of embedded applications. ...
FPGAs are generally employed to construct a reconfigurable block as it provides an instant timeto-market advantage. ...
PipeRench [19] is a dynamically reconfigurable architecture which allows configuration of processing elements to change in each execution cycle. ...
doi:10.5120/17254-7599
fatcat:fkhoir3wf5gp3et5fhmi5srifq
An Implementation of Multiple-Standard Video Decoder on a Mixed-Grained Reconfigurable Computing Platform
2016
IEICE transactions on information and systems
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3.6× performance gain over an industrial coarse-grained reconfigurable processor for H.264 decoding, and a 6.43× performance boosts over a general purpose processor based implementation for HEVC decoding ...
A soft-core-based microprocessor array is implemented on the FPGA and adopted to speed-up the dynamic reconfiguration of the RPU. ...
A dynamically reconfigurable processor named XPP-III, reported by Ganesan et al. [3] and Rossi et al. [4] , is an example of high-performance commercial reconfigurable multimedia processor. ...
doi:10.1587/transinf.2015edp7369
fatcat:4ixd2sywvvfv5izvwwhpzwl5xe
Dynamically Reconfigurable Embedded Architecture-An Alternative To Application-Specific Digital Signal Processing Architectures
2007
Journal of Computer Science
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To handle the conflicting requirements of being a flexible architecture and implement some application-specific algorithms, a dynamically reconfigurable embedded architecture is proposed. ...
This architecture combines a reconfigurable hardware processing unit with a software programmable processor. The main goal is to take advantage of the capabilities of both resources. ...
Dynamic reconfiguration is more relevant for a multi-context reconfigurable processing unit. ...
doi:10.3844/jcssp.2007.823.828
fatcat:qcgoqgtivnakjfexwobmhrynia
Temporal Performance Analysis of Enhanced 8 Bit RISC Architecture
2019
VOLUME-8 ISSUE-10, AUGUST 2019, REGULAR ISSUE
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We have designed the enhanced of 8 bit processor for improvement in speed as well as to speedup of the execution cycle, so that improvement in clock cycles per second for execution of an instruction. ...
The CALU is designed to enhance the multi-byte capabilities of the core. The performance improvement in terms of the clock cycle savings has been recorded. ...
After doing the above literature survey we a proposed an 8-bit RISC processor with co-operative arithmetic and logical unit. The proposed design will be more focuses on execution cycle saving. ...
doi:10.35940/ijitee.i8668.078919
fatcat:45zz4ugeizavljiderimypa5aq
Energy Efficient Multi-Core Processing
2014
Electronics
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The principles of the picoMIPS processor are illustrated with an example of the discrete cosine transform (DCT) and inverse DCT (IDCT) algorithms implemented in a multi-core context to demonstrate the ...
This paper evaluates the present state of the art of energy-efficient embedded processor design techniques and demonstrates, how small, variable-architecture embedded processors may exploit a run-time ...
The flexible heterogeneous Multi-Core processor (FMC) is an example of the fusion of these two architectures that can deliver both a high throughput for uniform parallel applications and high performance ...
doi:10.7251/els1418003l
fatcat:ehztmbwggvayddswnnp6qxg2ra
A Run-Time Task Migration Scheme for an Adjustable Issue-Slots Multi-core Processor
[chapter]
2012
Lecture Notes in Computer Science
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In this paper, we present a run-time task migration scheme for an adjustable/reconfigurable issue-slots very long instruction word (VLIW) multi-core processor. ...
The task migration scheme is realized with the implementation of interrupts on the ρ-VEX cores. The design is implemented in a Xilinx Virtex-6 FPGA. ...
Acknowledgment This work is supported by the European Commission in the context of the ERA (Embedded Reconfigurable Architectures) collaborative project #249059 (FP7). ...
doi:10.1007/978-3-642-28365-9_9
fatcat:fig2crumcrdqvg7iuxwtyxpkye
KAHRISMA: A Novel Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array Architecture
2010
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)
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In this paper we present our innovative processor architecture concept KAHRISMA (KArlsruhe's Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array). ...
As a consequence, next generation architectures for embedded systems have to react much more flexible to unforeseeable run-time scenarios. ...
Here, an FG-implementation would suffer from rather high reconfiguration time. ...
doi:10.1109/date.2010.5456939
dblp:conf/date/KoenigBSSABH10
fatcat:sx4exkhdqjfjbk7hb2bcx6biyq
Efficient dynamic reconfiguration for multi-context embedded FPGA
2008
Proceedings of the twenty-first annual symposium on Integrated circuits and system design - SBCCI '08
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Our solution is finally validated with the implementation of a WCDMA receiver on a multi-context embedded FPGA and demonstrates the interest and the efficiency of using dynamic reconfiguration. ...
Dynamic reconfiguration on fine-grained architecture can only be reached by multi-context FPGAs when reconfiguration time is a critical issue. ...
Thus, for an e-FPGA composed of a n · m array of logic cells, n · m · 20 clock cycles are needed to reconfigure the whole FPGA. This time is not acceptable for fast reconfiguration. ...
doi:10.1145/1404371.1404428
dblp:conf/sbcci/LalletPS08
fatcat:sauwtbhajfbjvinusk22a5cspq
RECONFIGURABLE FPGA BASED SOFT-CORE PROCESSOR FOR SIMD APPLICATIONS
2017
Asian Journal of Pharmaceutical and Clinical Research
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Thus the processor gives a significant computational cost of 12ms with a refresh rate of 60Hz and 1.29ns of MAC critical path delay.Conclusion:This FPGA based processor becomes a feasible solution for ...
This paper performs an analysis of FPGA (Field Programmable Gate Array) based high performance Reconfigurable OpenRISC1200 (ROR) soft-core processor for SIMD.Methods: The ROR1200 ensures performance improvement ...
ROR1200 reconfiguration explores compiler techniques to identify the number of registers essential for an application. ...
doi:10.22159/ajpcr.2017.v10s1.19632
fatcat:uu2crmcltvgdtparrdzwszig7u
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