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An automated exploration framework for FPGA-based soft multiprocessor systems

Yujia Jin, Nadathur Satish, Kaushik Ravindran, Kurt Keutzer
2005 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '05  
Using this tool, we implement a soft multiprocessor for IPv4 packet forwarding that achieves a throughput of 2 Gbps, surpassing the performance of a carefully tuned hand design.  ...  FPGA-based soft multiprocessors are viable system solutions for high performance applications. They provide a software abstraction to enable quick implementations on the FPGA.  ...  Deploying an application on the FPGA is tantamount to writing software for this multiprocessor system.  ... 
doi:10.1145/1084834.1084903 dblp:conf/codes/JinSRK05 fatcat:llzqhusnyrghlbu5vkh37dzsca

A Survey Approach - Multiprocessing on FPGA using Light Weight Processor
IJIREEICE - Electrical, Electronics, Instrumentation and Control

Shivaraja B G, Shankar B B, Praveen J, Raghavendra Rao A
Multiprocessor embedded systems (MESes) are a very promising approach for high performance yet relatively low-cost computing.  ...  This paper presents an implementation of a multiprocessing system on FPGA using multiple light weight soft processors (LWP) that work in conjunction with a custom hardware to achieve balanced performance  ...  A paper "An FPGA-based Soft Multi-processor System for IPv4 Packet Forwarding," [2] concluded on soft processing architecture obtains the effectiveness of FPGAbased soft-multiprocessors for high performance  ... 
doi:10.17148/ijireeice.2015.3303 fatcat:gzce4l6mi5aqhp4sexhqcmbcbi

ReClick - A Modular Dataplane Design Framework for FPGA-Based Network Virtualization

Deepak Unnikrishnan, Justin Lu, Lixin Gao, Russell Tessier
2011 2011 ACM/IEEE Seventh Symposium on Architectures for Networking and Communications Systems  
In this paper, we present ReClick, a framework to efficiently design and deploy reconfigurable dataplanes for FPGA-based network virtualization systems.  ...  Although recent research has highlighted field programmable gate arrays (FPGAs) as attractive platforms for high performance network virtualization, these devices remain inaccessible to the larger networking  ...  Programming Models for FPGA-based Packet Processing Systems Programmability is a key issue for FPGA-based packet processing systems.  ... 
doi:10.1109/ancs.2011.31 dblp:conf/ancs/UnnikrishnanLGT11 fatcat:7ue6erfkr5b4tmid5lasp7aww4

Application Specific Customization and Scalability of Soft Multiprocessors

Deepak Unnikrishnan, Jia Zhao, Russell Tessier
2009 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines  
[2] have illustrated the feasibility of using soft multiprocessors for a high performance IPv4 packet forwarding application.  ...  In this study, a framework to determine the best multiprocessor configuration for the data plane implementation of an IPv4 packet forwarding application using integer linear programming techniques is considered  ... 
doi:10.1109/fccm.2009.41 dblp:conf/fccm/UnnikrishnanZT09 fatcat:7cjy7ltl4rcyzlo7e2p4hdecdq

Scalable hardware monitors to protect network processors from data plane attacks

Kekai Hu, Harikrishnan Chandrikakutty, Russell Tessier, Tilman Wolf
2013 2013 IEEE Conference on Communications and Network Security (CNS)  
Modern router hardware in computer networks is based on programmable network processors, which implement various packet forwarding operations in software.  ...  We show the scalability of our monitoring system to network processors with large numbers of cores. We also present a multicore prototype implementation of the monitoring system on an FPGA platform.  ...  Fig. 11 .Fig. 12 .Fig. 13 . 111213 Simulation waveforms showing correct forwarding of an IPv4 packet. Simulation waveforms showing forwarding of an IPv4+CM packet.  ... 
doi:10.1109/cns.2013.6682721 dblp:conf/cns/HuCTW13 fatcat:wsfgq4pnb5akjmkvu7lzcr6gd4

Reconfigurable Multiprocessor Systems: A Review

Taho Dorta, Jaime Jiménez, José Luis Martín, Unai Bidarte, Armando Astarloa
2010 International Journal of Reconfigurable Computing  
Modern digital systems demand increasing electronic resources, so the multiprocessor platforms are a suitable solution for them.  ...  Advances in FPGA technology are leading to more powerful systems in terms of processing and flexibility.  ...  Acknowledgments This work has been supported by the Department of Education, Universities and Research of the Basque Government within the fund for research groups of the Basque university system IT394  ... 
doi:10.1155/2010/570279 fatcat:uho74omrjzbjhe5nwm36zupxam

Analysis of a reconfigurable network processor

C. Kachris, S. Vassiliadis
2006 Proceedings 20th IEEE International Parallel & Distributed Processing Symposium  
Furthermore, the results of two case studies are presented, for a soft-and a hard-IP core processor, that uses three flows with different processing requirements (IP forward, encryption and media processing  ...  In this paper an analysis of a dynamically reconfigurable processor is presented.  ...  an FPGA.  ... 
doi:10.1109/ipdps.2006.1639430 dblp:conf/ipps/KachrisV06 fatcat:vbyclieou5dl3j4oxssdilrvaq

Performance comparison between the Click Modular Router and the NetFPGA Router

Leonardo Linguaglossa, Alfio Lombardo, Diego Reforgiato, Giovanni Schembra
2011 International Journal of Computer Networks & Communications  
NetFPGA reference designs comprised in the system include an IPv4 router, an Ethernet switch, a fourport NIC, and SCONE (Software Component of NetFPGA).  ...  1 It is possible to forward minimum-sized packets at rates of hundreds of Mbps using commodity hardware and Linux.  ...  ACKNOWLEDGEMENTS The authors would like to thank the reviewers for improved the quality of the paper.  ... 
doi:10.5121/ijcnc.2011.3503 fatcat:crj65hieqjfwrmru2q7xh4reje

An Energy-Efficient FPGA-Based Packet Processing Framework [chapter]

Dániel Horváth, Imre Bertalan, István Moldován, Tuan Anh Trinh
2010 Lecture Notes in Computer Science  
In this paper we present an architecture for high-speed packet processing with a hierarchical chip-level power management that minimizes the energy consumption of the system.  ...  In particular, we present a modeling framework that provides an easy way to create new networking applications on an FPGA based board.  ...  [1] on the design of lookup machine of a hardware router for IPv6 and IPv4 packet routing with operations are performed by FPGA, since FPGA-based implementations are an attractive option for implementing  ... 
doi:10.1007/978-3-642-13971-0_4 fatcat:6lst5fvzynfk7ligkbrgg2wtom

Design of a web switch in a reconfigurable platform

Christoforos Kachris, Stamatis Vassiliadis
2006 Proceedings of the 2006 ACM/IEEE symposium on Architecture for networking and communications systems - ANCS '06  
The system supports the TCP splicing scheme to accelerate the routing of the packets by forwarding packets at the IP layer after a connection has been spliced.  ...  Hence, the system provides an efficient combination of processor's flexibility and ASIC's performance.  ...  Another option is the switching based on the application. For example the HTTP request for an image could be forwarded to a separate server than the server for the HTML pages.  ... 
doi:10.1145/1185347.1185352 dblp:conf/ancs/KachrisV06 fatcat:y7qtwgifwvcgzfzoudbgarel5i

Design space exploration using arithmetic-level hardware--software cosimulation for configurable multiprocessor platforms

Jingzhao Ou, Viktor K. Prasanna
2006 ACM Transactions on Embedded Computing Systems  
Configurable multiprocessor platforms consist of multiple soft processors configured on FPGA devices. They have become an attractive choice for implementing many computing applications.  ...  For illustrative purposes, we provide an implementation of our approach based on MATLAB/Simulink.  ...  The authors would also like to thank Phil James-Roxby for offering us the original VHDL multiprocessor design of the JPEG2000 application.  ... 
doi:10.1145/1151074.1151080 fatcat:4h5l2jh5crdwnpktv2m7vepki4

Parallel embedded processor architecture for FPGA-based image processing using parallel software skeletons

Hanen Chenini, Jean Pierre Dérutin, Romuald Aufrère, Roland Chapuis
2013 EURASIP Journal on Advances in Signal Processing  
Today, the problem of designing suitable multiprocessor architecture tailored for a target application field raises the need for a fast and efficient multiprocessor system-on-chip (MPSoC) design environment  ...  Then, we extend our approach to support more complex applications by implementing a soft multiprocessor for 'multihypotheses model-driven approach for road recognition' and show the impact of various configuration  ...  Using this tool, we implement a soft multiprocessor for IPv4 packet forwarding that achieves a throughput of 2 Gbps.  ... 
doi:10.1186/1687-6180-2013-153 fatcat:hx27il6bx5bsplgjffgqqj6xlu

An FPGA-based soft multiprocessor system for IPV 4 packet forwarding

K. Ravindran, N. Satish, Yujia Jin, K. Keutzer
International Conference on Field Programmable Logic and Applications, 2005.  
We deploy IPv4 packet forwarding on a multiprocessor on the Xilinx Virtex-II Pro FPGA.  ...  This also opens FPGAs to the world of software designers. In this paper, we demonstrate the feasibility of FPGA-based multiprocessors for high performance applications.  ...  Fig. 1 . 1 Data Plane of the IPv4 packet forwarding application. Fig. 2 . 2 Soft multiprocessor system for the data plane of the IPv4 packet forwarding application.  ... 
doi:10.1109/fpl.2005.1515769 dblp:conf/fpl/RavindranSJK05 fatcat:xvyorxvzh5f77ngqk4rhweruhi

Vector Processing as a Soft Processor Accelerator

Jason Yu, Christopher Eagleston, Christopher Han-Yu Chou, Maxime Perreault, Guy Lemieux
2009 ACM Transactions on Reconfigurable Technology and Systems  
core and multiple vector lanes Three ways of accelerating FPGA-based applications with plenty of data-level parallelism are: 1) build a multiprocessor system and write parallel code, or 2) build a dedicated  ...  This paper introduces VIPERS, a soft vector processor architecture that maps efficiently into an FPGA and provides a scalable amount of performance for a reasonable amount of area.  ...  For example, the IPv4 packet forwarding system in [Ravindran et al. 2005 ] has 14 MicroBlaze processors and two hard core PowerPC processors arranged in four parallel processor pipelines with each stage  ... 
doi:10.1145/1534916.1534922 fatcat:bwu777f7onbn5j5tptvztpmho4

System-level security for network processors with hardware monitors

Kekai Hu, Tilman Wolf, Thiago Teixeira, Russell Tessier
2014 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)  
Modern routers use programmable network processors that may be exploited by merely sending suitably crafted data packets into a network.  ...  We have demonstrated to operation of our system in hardware on an FPGA-based platform.  ...  System Setup We have implemented a prototype SDMMon in an Altera Stratix IV FPGA on an Altera DE4 board.  ... 
doi:10.1109/dac.2014.6881538 fatcat:ortoqu7hgbgwxdphc7w2douwb4
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