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Guest Editors' Introduction: Configurable computing

F.J. Kurdahi, N. Bagherzadeh, P. Athanas, J.L. Munoz
2000 IEEE Design & Test of Computers  
Peter Athanas is an associate professor in the Bradley Department of Electrical and Computer Engineering at Virginia Tech. His research interests focus on configurable computing and microslwtronics.  ...  Coniigurable computing machines (CCMs) are emerging as a technology capable of providing high computational performance on a diversity of applications, including ID and 2D signal processing, image processing  ...  Third, configurable computing embedded solutions can fold in many of the sensor/actuator prcconditioning and "glue logic" functions on a chip.  ... 
doi:10.1109/mdt.2000.825673 fatcat:7knsnwp7dngttn6cuurrw3obxu

Mapping Processing Elements of Custom Virtual CGRAs onto Reconfigurable Partitions

Zbigniew Mudza, Rafał Kiełbik
2022 Electronics  
These problems can be mitigated by implementing a coarser overlay atop the FPGA fabric.  ...  Module relocation can be used to share implementation details between functionally equivalent PEs that use identical sets of resources, thus eliminating redundant placement and routing runs.  ...  Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/electronics11081261 fatcat:3hfoim4lobfcrlb45fsacmfrjq

Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug

Yousef S. Iskander, Cameron D. Patterson, Stephen D. Craven
2011 2011 21st International Conference on Field Programmable Logic and Applications  
interface directly to a running design on an FPGA.  ...  The second approach provides an alternative view to FPGAs within the scope of a traditional software debugger.  ...  Low-Level Debug (LLD) changes the perspective of FPGA debugging from an external viewpoint to an internal one, removing much of the latency and design-time commitments from debugging.  ... 
doi:10.1109/fpl.2011.102 dblp:conf/fpl/IskanderPC11 fatcat:3m3crbq42remvh6d7oz6ftpexu

Efficient Edge-AI Application Deployment for FPGAs

Stavros Kalapothas, Georgios Flamis, Paris Kitsos
2022 Information  
The platform supports the Python-based PYNQ framework and maintains a high level of versatility with the support of custom bitstreams (overlays).  ...  a Zynq multiprocessor system-on-chip (MPSoC).  ...  PYNQ [8] , is an additional open source and very modifiable framework with a Pythonbased programming interface for high level synthesis and rapid CNN/DNN prototyping on FPGAs with a Zynq system-on-chip  ... 
doi:10.3390/info13060279 fatcat:ecw2przphze6jltbk6wxtbstku

FPGA Technology and Dynamic Reconfiguration [chapter]

2009 Reconfigurable System Design and Verification  
Reconfiguring an FPGA means changing its functionality to support a new application, and it is equal to have some new piece of hardware -mapped on the FPGA chip -to implement a new functionality.  ...  an architecture on FPGA, but not of particular guidance when this module based design is used to implement a PDR architecture.  ...  A first opportunity is the addition of new devices and families to the framework: provided the underlying architectural description of new FPGA devices does not change radically, it will be possible to  ... 
doi:10.1201/9781420062670.ch2 fatcat:gx7k4xvydvhkboa7rodcburqia

On Predictable Reconfigurable System Design

Nils Voss, Bastiaan Kwaadgras, Oskar Mencer, Wayne Luk, Georgi Gaydadjiev
2021 ACM Transactions on Architecture and Code Optimization (TACO)  
As a result the architectures were implemented first time right, achieving state-of-the-art performance within 15% of our modelling estimations.  ...  Our methodology relies on analytical estimation of system performance and area utilisation for a given specific application and a particular system instance consisting of a controlflow machine working  ...  Using the same API for the software model as for the FPGA implementation also creates an easyto-use debugging tool for the FPGA implementation.  ... 
doi:10.1145/3436995 fatcat:w3lkr776lbb5to4d3v6tfq7ftq

State-of-the-art in Heterogeneous Computing

Andre R. Brodtkorb, Christopher Dyken, Trond R. Hagen, Jon M. Hjelmervik, Olaf O. Storaasli
2010 Scientific Programming  
We give an overview of the state-of-the-art in heterogeneous computing, focusing on three commonly found architectures: the Cell Broadband Engine Architecture, graphics processing units (GPUs), and field  ...  Furthermore, we present a qualitative and quantitative comparison of the architectures, and give our view on the future of heterogeneous computing.  ...  We also appreciate the valuable input from the anonymous reviewers, and the continued support from AMD, IBM, and NVIDIA.  ... 
doi:10.1155/2010/540159 fatcat:xu4n5ubgfzh3bobd445cmg7qyu

ADAM

Ho-Cheung Ng, Shuanglong Liu, Wayne Luk
2018 Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays - FPGA '18  
This paper introduces ADAM, an approach for merging multiple FPGA designs into a single hardware design, so that multiple placeand-route tasks can be replaced by a single task to speed up functional evaluation  ...  of designs, especially during the development process.  ...  ACKNOWLEDGMENT The support of the Lee Family Scholarship, the EU Horizon 2020 Research and Innovation Programme under grant agreement number 671653 and the UK EPSRC (EP/L00058X/1, EP/L016796/1, EP/N031768  ... 
doi:10.1145/3174243.3174247 dblp:conf/fpga/NgLL18 fatcat:xugrgidax5hm7eounibvahlbja

Dynamic hardware video processing platform

Ray Andraka, John Schewel, Peter M. Athanas, V. Michael Bove, Jr., John Watson
1996 High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic  
The use of a common framework with application overlays also allows the designer to concentrate on the image processing algorithm instead of worrying about the background functions.  ...  Algorithm changes at the frame rate are made possible with high speed and partial reconfiguration.  ...  The board is host to an FCM reconfigurable multi-chip module. To support that module, the board contains a hardwired ISA interface (BT & BC in Figure 2 ) and an additional CLAy 31 logic array.  ... 
doi:10.1117/12.255806 fatcat:ouza2y6hwfawfen2nsmcjomqty

Adaptive Computing in Robotics, Leveraging ROS 2 to Enable Software-Defined Hardware for FPGAs [article]

Víctor Mayoral-Vilches, Giulio Corradi
2021 arXiv   pre-print
This white paper adopts a ROS 2 roboticist-centric view for adaptive computing and proposes an architecture to include FPGAs as a first-class participant of the ROS 2 ecosystem.  ...  Traditional software development in robotics is about programming functionality in the CPU of a given robot with a pre-defined architecture and constraints.  ...  FPGAs can be used for virtually any processing task in robotics since it is possible to implement parallel processing on an FPGA in addition to implementing other processing architectures.  ... 
arXiv:2109.03276v1 fatcat:uqtcnikppbcwzcfyckcwuvxxtm

Direct Universal Access: Making Data Center Resources Available to FPGA

Ran Shu, Peng Cheng, Guo Chen, Zhiyuan Guo, Lei Qu, Yongqiang Xiong, Derek Chiou, Thomas Moscibroda
2019 Symposium on Networked Systems Design and Implementation  
We also build two practical multi-FPGA applications-deep crossing and regular expression matching-on top of DUA to demonstrate its usability and efficiency.  ...  In this paper, we present Direct Universal Access (DUA), a communication architecture that provides uniform access for FPGA to these data center resources.  ...  Poor Resource Multiplexing: To support accessing data center resources as a pool, resource multiplexing is one of the key considerations of an FPGA communication architecture.  ... 
dblp:conf/nsdi/Shu0CGQXCM19 fatcat:jvyawmz7tzhqnn4kkk4q66tqcq

Synthesizable FPGA fabrics targetable by the Verilog-to-Routing (VTR) CAD flow

Jin Hee Kim, Jason H. Anderson
2015 2015 25th International Conference on Field Programmable Logic and Applications (FPL)  
The proposed framework and methodology opens the door to silicon implementation of a wide range of VTR-modelled FPGA fabrics.  ...  In an experimental study, area and timing-optimized FPGA implementations in 65nm TSMC standard cells are compared with a 65nm Altera commercial FPGA.  ...  The inputs to VTR are: 1) a description of an FPGA architecture, and 2) an application benchmark for implementation in the FPGA.  ... 
doi:10.1109/fpl.2015.7293955 dblp:conf/fpl/KimA15 fatcat:wrsq6lssqvbyvbu4gr7wbuuc6m

FPGA Acceleration for Big Data Analytics: Challenges and Opportunities

Joost Hoozemans, Johan Peltenburg, Fabian Nonnemacher, Akos Hadnagy, Zaid Al-Ars, H. Peter Hofstee
2021 IEEE Circuits and Systems Magazine  
FPGAs allow the implementation of highly optimized hardware architectures, tailored exactly to an application, and unburdened by the overhead associated with traditional general-purpose computer architectures  ...  FPGAs implementing dataflow-oriented architectures with high levels of (pipeline) parallelism can provide high application throughput, often providing high energy efficiency.  ...  The authors also thank Patrick Lysaght and Cathal McCabe from Xilinx for their support.  ... 
doi:10.1109/mcas.2021.3071608 fatcat:ywvymvx6bvc4dhytbgjcoqov2u

Isolation mechanisms for high-speed packet-processing pipelines [article]

Tao Wang, Xiangrui Yang, Gianni Antichi, Anirudh Sivaraman, Aurojit Panda
2022 arXiv   pre-print
Finally, we demonstrate that feasibility of implementing Menshen on ASICs by using the FreePDK45nm technology library and the Synopsys DC synthesis software, showing that our design meets timing at a 1GHz  ...  We have prototyped Menshen on two FPGA platforms (NetFPGA and Corundum). We show that our design provides isolation, and allows new modules to be loaded without impacting the ones already running.  ...  We thank Han Wang and Anurag Agrawal with whom we discussed the Tofino architecture, and Alex Forencich, the FlowBlaze and NetFPGA teams, who helped us with debugging and design.  ... 
arXiv:2101.12691v4 fatcat:als2ow34ujej7pmw3tnkttcf7q

The Potential for a GPU-Like Overlay Architecture for FPGAs

Jeffrey Kingyens, J. Gregory Steffan
2011 International Journal of Reconfigurable Computing  
Through simulation of a system that (i) is programmable via NVIDIA's high-levelCglanguage, (ii) supports AMD's CTM r5xx GPU ISA, and (iii) is realizable on an XtremeData XD1000 FPGA-based accelerator system  ...  In particular, our soft processor architecture exploits multithreading, vector operations, and predication to supply a floating-point pipeline of 64 stages via hardware support for up to 256 concurrent  ...  We therefore require the central register file to support 8 KB of on-chip memory per batch.  ... 
doi:10.1155/2011/514581 fatcat:kiakbzjtjzh5jnref7xatxl3fy
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