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Measuring the Impact of Memory Errors on Application Performance

Mark Gottscho, Mohammed Shoaib, Sriram Govindan, Bikash Sharma, Di Wang, Puneet Gupta
2017 IEEE computer architecture letters  
We focus on a common third scenario, namely, situations when hard but correctable faults exist in memory; these may cause an "avalanche" of errors to occur on affected hardware.  ...  For an interactive web-search workload, average query latency degrades by up to 2.3× for a light traffic load, and up to an extreme 3746× under peak load.  ...  (Note that forms of memory scrubbing may also cause additional performance degradation in presence of errors, but these were not evaluated due to experimental limitations in our fault injection framework  ... 
doi:10.1109/lca.2016.2599513 fatcat:lmnmtq2zdjdm5fak2zaieyzjsi

SWL

Jihyun In, Ilhoon Shin, Hyojun Kim
2007 SIGPLAN notices  
In this paper, we present a method that reduces the long latency of page faults by performing page fault handling in a parallelized manner, considering the characteristics of NAND-Type flash memory.  ...  Experimental results show that the parallelized page fault handler improves the worst case latency of page faults significantly, by up to roughly 20%, and that the modified page cache replacement policies  ...  In our experimental configuration, the latency of a false fault in FIFO-SC was measured to be 14.3 us on average.  ... 
doi:10.1145/1273444.1254806 fatcat:77krln3bxzb5lmpburvpuq6cue

SWL

Jihyun In, Ilhoon Shin, Hyojun Kim
2007 Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools - LCTES '07  
In this paper, we present a method that reduces the long latency of page faults by performing page fault handling in a parallelized manner, considering the characteristics of NAND-Type flash memory.  ...  Experimental results show that the parallelized page fault handler improves the worst case latency of page faults significantly, by up to roughly 20%, and that the modified page cache replacement policies  ...  In our experimental configuration, the latency of a false fault in FIFO-SC was measured to be 14.3 us on average.  ... 
doi:10.1145/1254766.1254806 dblp:conf/lctrts/InSK07 fatcat:bnkfspcmmfgfpgjphihq3nbazy

Dependability evaluation and benchmarking of Network Function Virtualization Infrastructures

Domenico Cotroneo, Luigi De Simone, Antonio Ken Iannillo, Anna Lanzaro, Roberto Natella
2015 Proceedings of the 2015 1st IEEE Conference on Network Softwarization (NetSoft)  
Network Function Virtualization (NFV) is an emerging solution that aims at improving the flexibility, the efficiency and the manageability of networks, by leveraging virtualization and cloud computing  ...  In this paper, we propose a methodology for the dependability evaluation and benchmarking of NFV Infrastructures (NFVIs), based on fault injection.  ...  CASE STUDY To show the application of the dependability evaluation methodology, we perform an experimental analysis of a virtualized IP Multimedia Subsystem (IMS) deployed over an NFVI.  ... 
doi:10.1109/netsoft.2015.7116123 dblp:conf/netsoft/CotroneoSILN15 fatcat:hnvqxb7bvnhlvoutu7kfrfcijm

Design and implementation of user-level remote memory extension library

Shinyoung Ahn, Gyuil Cha, Youngho Kim, Eunji Lim
2015 2015 17th International Conference on Advanced Communication Technology (ICACT)  
The increase of memory capacity has not kept up with the continuous increase of large memory applications.  ...  From the experimental test, we found that user-level remote memory extension library works well for applications with sequential access pattern.  ...  AN EXPERIMENTAL STUDY We wrote a Remote Memory Library which handle userlevel page fault and manage temporal page pools and provide user-level API.  ... 
doi:10.1109/icact.2015.7224893 fatcat:e3dqro4y4nfktor3sujt6cwbii

SoftSNN: Low-Cost Fault Tolerance for Spiking Neural Network Accelerators under Soft Errors [article]

Rachmad Vidya Wicaksana Putra, Muhammad Abdullah Hanif, Muhammad Shafique
2022 arXiv   pre-print
The experimental results show that, for a 900-neuron network with even a high fault rate, our SoftSNN maintains the accuracy degradation below 3%, while reducing latency and energy by up to 3x and 2.3x  ...  However, the impact of soft errors in the compute engine and the respective mitigation techniques have not been thoroughly studied yet for SNNs.  ...  Latency: Experimental results for latency are shown in Fig. 14(a) .  ... 
arXiv:2203.05523v2 fatcat:tllymlkopzfozcnnx3nhycnurm

Edge Computing-based Fault-Tolerant Framework: A Case Study on Vehicular Networks

Asad Javed, Avleen Malhi, Kary Framling
2020 2020 International Wireless Communications and Mobile Computing (IWCMC)  
Due to unreliable communications in vehicular networks, implementing fault-tolerant techniques for the Road Side Unit (RSU) infrastructure is an imperial need.  ...  Within this context, the contributions of this paper are twofold: (i) we propose a distributed fault-tolerant framework for V2I and I2I communications based on edge computing to resolve hardware-and network  ...  ACKNOWLEDGEMENTS This work has received funding from the European Union's Horizon 2020 research and innovation programme (grant 688203) and Academy of Finland (Open Messaging Interface; grant 296096).  ... 
doi:10.1109/iwcmc48107.2020.9148269 dblp:conf/iwcmc/JavedMF20 fatcat:hp2iz2zl7jglhibzcu7rw75ara

Automatic compiler-inserted I/O prefetching for out-of-core applications

Todd C. Mowry, Angela K. Demke, Orran Krieger
1996 Proceedings of the second USENIX symposium on Operating systems design and implementation - OSDI '96  
Our experimental results demonstrate that our fully-automatic scheme effectively hides the I/O latency in out-ofcore versions of the entire NAS Parallel benchmark suite, thus resulting in speedups of roughly  ...  As a result, programmers who wish to solve "out-of-core" problems efficiently are typically faced with the onerous task of rewriting an application to use explicit I/O operations (e.g., read/write).  ...  Acknowledgments We thank the entire Hurricane and Hector research teams for developing this experimental platform.  ... 
doi:10.1145/238721.238734 dblp:conf/osdi/MowryDK96 fatcat:4fn4iw2qpzfxlokt3ksperikmi

Automatic compiler-inserted I/O prefetching for out-of-core applications

Todd C. Mowry, Angela K. Demke, Orran Krieger
1996 ACM SIGOPS Operating Systems Review  
Our experimental results demonstrate that our fully-automatic scheme effectively hides the I/O latency in out-ofcore versions of the entire NAS Parallel benchmark suite, thus resulting in speedups of roughly  ...  As a result, programmers who wish to solve "out-of-core" problems efficiently are typically faced with the onerous task of rewriting an application to use explicit I/O operations (e.g., read/write).  ...  Acknowledgments We thank the entire Hurricane and Hector research teams for developing this experimental platform.  ... 
doi:10.1145/248155.238734 fatcat:kp2avlnrbbcq3e4zqm3eqqaike

Diverse Partial Memory Replication

Ryan M. Lefever, Vikram S. Adve, William H. Sanders
2010 2010 IEEE/IFIP International Conference on Dependable Systems & Networks (DSN)  
DPMR is an automatic compiler transformation that replicates some subset of an executable's data memory and applies one or more diversity transformations to the replica.  ...  DPMR can detect any kind of memory safety errors in any part of a program's data memory.  ...  Any opinions, findings, and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the National Science Foundation.  ... 
doi:10.1109/dsn.2010.5545012 dblp:conf/dsn/LefeverAS10 fatcat:q7akjpphuraflmezwqy6eg7mee

Fault injection experiments using FIAT

J.H. Barton, E.W. Czeck, Z.Z. Segall, D.P. Siewiorek
1990 IEEE transactions on computers  
For a discussion of how two or more tools such as ARIES and HARP complement each other in evaluating a fault-tolerant system, we refer the reader to 183. ~41. REFERENCES [I] S .  ...  As mentioned in the Introduction, several mathematical models for predicting the behavior of fault-tolerant systems (for example, ARIES, CARE-111, HARP, SAVE, and SURF) are currently available.  ...  Comparison to Experimental Data: A static analysis of the memory image was performed, and an examination of the experiments yielded the number of faults injected into opcode fields.  ... 
doi:10.1109/12.54853 fatcat:c257amombrdtdd6cakereg2f2q

Memorage

Ju-Young Jung, Sangyeun Cho
2013 Proceedings of the 27th international ACM conference on International conference on supercomputing - ICS '13  
Under memory pressure, the performance of studied memory-intensive multiprogramming workloads was improved by up to 40.5% with an average of 16.7%.  ...  We design and implement a prototype system in the Linux OS to study the effectiveness of Memorage.  ...  Software Latency of a Page Fault In this section, we obtain and report two latencies, one for "fast path" (taken for a minor fault) and another for "slow path" (major fault).  ... 
doi:10.1145/2464996.2465005 dblp:conf/ics/JungC13 fatcat:x7dqktrnz5hgni54ecf6rdauja

Fine-Grained Characterization of Faults Causing Long Latency Crashes in Programs

Guanpeng Li, Qining Lu, Karthik Pattabiraman
2015 2015 45th Annual IEEE/IFIP International Conference on Dependable Systems and Networks  
We first identify program code patterns that are responsible for the majority of LLC causing faults through an empirical study.  ...  An important class of faults are those that cause longlatency crashes (LLCs), or faults that can persist for a long time in the program before causing it to crash.  ...  We thank the Institute of Computing, Information and Cognitive Systems (ICICS) at the University of British Columbia for travel support.  ... 
doi:10.1109/dsn.2015.36 dblp:conf/dsn/LiLP15 fatcat:qq4u2llj55bzhfidt5yab7dzxm

Checkpointing virtual machines against transient errors

Long Wang, Zbigniew Kalbarczyk, Ravishankar K. Iyer, Arun Iyengar
2010 2010 IEEE 16th International On-Line Testing Symposium  
In our approach, knowledge of fault/error latency is used to explicitly address checkpoint corruption, a critical problem, especially when checkpoint frequency is high.  ...  The evaluation results demonstrate that VM-µCheckpoint incurs an average of 6.3% execution-time overhead for 50ms checkpoint intervals when executing the SPEC CINT 2006 benchmark.  ...  An experimental assessment of VM-µCheckpoint using (i) SPEC benchmark programs.  ... 
doi:10.1109/iolts.2010.5560226 dblp:conf/iolts/WangKII10 fatcat:xxmwf5bmkbd3hijf6a5d3gowea

CARAT: Context-aware runtime adaptive task migration for multi core architectures

J Jahn, M A A Faruque, J Henkel
2011 2011 Design, Automation & Test in Europe  
This novel mechanism is built on an in-depth analysis of the memory access behavior of several multi-media and robotic embedded-systems applications. †  ...  For distributed memory architectures, the policy for transferring the task context between source and destination cores is of vital importance to the performance and to the successful operation of the  ...  Section IV presents the details and algorithm used in CARAT guided by a memory access behavior study, followed by experimental results, with their interpretation concluding this paper in Section VI.  ... 
doi:10.1109/date.2011.5763093 dblp:conf/date/JahnFH11 fatcat:ju2kv4ilpnbbvmczcs6w7dffvi
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