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Exploring Potential Benefits of 3D FPGA Integration [chapter]

Cristinel Ababei, Pongstorn Maidee, Kia Bazargan
2004 Lecture Notes in Computer Science  
We show that 3D integration results in wire-length reduction for FPGA designs.  ...  Our empirical analysis shows that wire-length can be reduced by up to 50% (20% on average) using 5 layers.  ...  Interlayer via minimization is sought by min-cut partitioning for layer assignment. Wire-length minimization is done by considering aspect ratio during the partitioning.  ... 
doi:10.1007/978-3-540-30117-2_92 fatcat:pd3daploc5fnllv2xewgqlq3ym

An exact algorithm for coupling-free routing

Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh
2001 Proceedings of the 2001 international symposium on Physical design - ISPD '01  
We develop an exact algorithm for the CFR decision problem via a transformation to 2-satisfiability. This algorithm runs in linear time.  ...  Finally, we develop a new algorithm for the Maximum Coupling-Free Layout (MAX-CFL) problem. Given a set of nets, the MAX-CFL is defined as finding a subset of nets that are coupling-free routable.  ...  An exact algorithm for Coupling-Free Routing Decision Problem (CFRDP) is given in Section 3. The implication graph is presented in Section 4.  ... 
doi:10.1145/369691.369711 dblp:conf/ispd/KastnerBS01 fatcat:k74qdlhwu5gjxlqykd26ixnlpy

Performance Analysis of the Algorithms forthe Construction of Multilayer Obstacle Avoiding Rectilinear Steiner Minimum Tree

Divyaprabha Divyaprabha, Dr. Prasad G.R
2014 IOSR Journal of Electrical and Electronics Engineering  
reduced wire length) in less running time.  ...  This paper provides a survey of various multilayer obstacles avoiding rectilinear Steiner minimal tree algorithms proposed and thus there is a need for an algorithm to produce better solution quality (  ...  Algorithm-3 Iris Hui-Ru Jiang [7] has proposed a unified algorithm to solve both single and multiple routing layers. Exact algorithm-1 uses connection graph based approach.  ... 
doi:10.9790/1676-09610512 fatcat:sgwwxg3rmrgfhpw6j75ruvfsju

DUNE-a multilayer gridless routing system

J. Cong, Jie Fang, Kei-Yong Khoo
2001 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Our detailed routing system also features a coarse grid-based wire-planning algorithm that uses exact gridless design rules (variable-width and variable-spacing) to accurately estimate the routing resources  ...  Our detailed routing system users a hybrid approach consisting of two parts: 1) an efficient variable-width variable-spacing detailed routing engine and 2) a wire-planning algorithm providing high-level  ...  ACKNOWLEDGMENT The authors would like to thank their colleagues at the UCLA VLSI CAD Laboratory for the discussion and especially P. Madden, C.-C. Chang, and D. Pan for their contributions.  ... 
doi:10.1109/43.920694 fatcat:4ei7nrcrkzbrrlupxco7vvb6ka

EWA

Rony Kay, Gennady Bucheuv, Lawrence T. Pileggi
1997 Proceedings of the 1997 international symposium on Physical design - ISPD '97  
In this paper the EWA algorithm is described. It solves the problem of minimizing the wiring area or capacitance of an interconnect tree subject to constraints on the Elmore delay.  ...  The wire sizing problem under inequality Elmore delay constraints is known to be posynomial, hence convex under an exponential variable-transformation.  ...  The monotonicity makes sense and can be proved for a single layer wiring; it does not hold for deep submicron technologies and multi-layer wiring, where the unit resistivity and unit-capacitance vary significantly  ... 
doi:10.1145/267665.267710 dblp:conf/ispd/KayBP97 fatcat:a22uru6tandqzddwjmcfbfdlvu

Octilinear redistributive routing in bump arrays

Renshen Wang, Chung-Kuan Cheng
2009 Proceedings of the 19th ACM Great Lakes symposium on VLSI - GLSVLSI '09  
This paper proposes a scheme for automatic re-distribution layer (RDL) routing, which is used in chip-package connections.  ...  In this paper we devise a polynomial time octilinear RDL routing algorithm based on a grid network embedded in the bump array.  ...  a single layer.  ... 
doi:10.1145/1531542.1531591 dblp:conf/glvlsi/WangC09 fatcat:ckovzsy7hzhlzc2z3glh6fag74

3D IC optimal layout design. A parallel and distributed topological approach [article]

Katarzyna Grzesiak-Kopeć, Maciej Ogorzałek
2019 arXiv   pre-print
The presented approach uses an original 3D layout graph partitioning heuristics implemented with use of the extremal optimization method. The goal is to minimize the total wire-length in the chip.  ...  It is a NP-hard problem that requires new non-deterministic and heuristic algorithms.  ...  Conclusions This article presents an original and general 3-step intelligent approach to the total wire-length minimization in the integrated circuits design.  ... 
arXiv:1911.11768v1 fatcat:gb4thpenjba3nho2dw24cpkpee

Customized Routing Optimization Flow to Fix Timing Violations in Ultra Deep Sub Micron Technology

Omkar Deshkar
2020 2020 Third International Conference on Advances in Electronics, Computers and Communications (ICAECC)  
In ultra-deep sub-micron technology, Routing has become challenging due to ever increasing number of metal layers, distinct layer thicknesses, new design rules and design complexity.  ...  with DRC clean and without degrading post layout timings.Area reduction with lower node technology, routing congestion increases on chip and in that scenario need to route the best topology with metal layers  ...  Karan Patel for all constant guidance and support throughout the work. I am thankful to Dr.  ... 
doi:10.1109/icaecc50550.2020.9339482 fatcat:vgers7zozbd7zotnpcwbm2fnv4

Advances in PCB Routing

Tan Yan, Qiang Ma, Martin D.F. Wong
2012 IPSJ Transactions on System LSI Design Methodology  
In this paper, we provide an overview of recent research results on the PCB routing problem.  ...  We focus on the escape routing problem and the length-matching routing problem, which are the two most important problems in PCB routing. Other relevant works are also briefly introduced.  ...  In a later work, Ozdal and Wong [35] , [36] proposed an algorithm for length-matching routing inside a channel.  ... 
doi:10.2197/ipsjtsldm.5.14 fatcat:5sjgv26znra7ji32vyr5gfjo5u

Recent research development in PCB layout

Tan Yan, Martin D. F. Wong
2010 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)  
In this paper, we provide an overview of recent research results on the PCB layout problem.  ...  We focus on the escape routing problem and the length-matching routing problem, which are the two most important problems in PCB layout.  ...  In a later work, Ozdal and Wong [30] , [31] proposed an algorithm for length-matching routing inside a channel.  ... 
doi:10.1109/iccad.2010.5654190 dblp:conf/iccad/YanW10 fatcat:l3sjdaymt5h55mgbldvl2763x4

The Complexity of Design Automation Problems [chapter]

Sartaj Sahni, Atul Bhatt, Raghunath Raghavan
1988 Handbook of Advanced Semiconductor Technology and Computer Systems  
Secondly, labor-intensive methods do not adequately accomodate the increasingly more stringent requirements for an acceptable design.  ...  This points out the importance of heuristics and other tools to obtain algorithms that perform well on the problem instances of interest. . +++ Address: Mentor Graphics, Beaverton, OR 97005.  ...  Since the notion of a step is somewhat inexact, one often does not strive to obtain an exact step count for an algorithm. Rather, asymptotic bounds on the step count are obtained.  ... 
doi:10.1007/978-94-011-7056-7_17 fatcat:muwhoo6fgvfdlmszv4wheza53q

The complexity of design automation problems

Sartaj Sahni, Atul Bhatt
1980 Proceedings of the seventeenth design automation conference on Design automation - DAC '80  
Secondly, labor-intensive methods do not adequately accomodate the increasingly more stringent requirements for an acceptable design.  ...  This points out the importance of heuristics and other tools to obtain algorithms that perform well on the problem instances of interest. . +++ Address: Mentor Graphics, Beaverton, OR 97005.  ...  Since the notion of a step is somewhat inexact, one often does not strive to obtain an exact step count for an algorithm. Rather, asymptotic bounds on the step count are obtained.  ... 
doi:10.1145/800139.804562 dblp:conf/dac/SahniB80 fatcat:h427snpf35gjdhub6ugvxkfpza

Mathematical methods for physical layout of printed circuit boards: an overview

Nadine Abboud, Martin Grötschel, Thorsten Koch
2007 OR spectrum  
This article surveys mathematical models and methods used for the physical layout of printed circuit boards, in particular component placement and wire routing.  ...  Ozdal and Wong (2004a) describe an algorithm for high performance single-layer bus routing, where the objective is to match the lengths of all nets belonging to each bus.  ...  A widely used objective in practice is to minimize the total wire length of all connections. Unfortunately, the exact wire length of each net is not known until the nets are actually routed.  ... 
doi:10.1007/s00291-007-0080-9 fatcat:foqsqskbovgl3jif4wijlcajsm

Partitioning and placement for buildable QCA circuits

Ramprasad Ravichandran, Mike Niemier, Sung Kyu Lim
2005 Proceedings of the 2005 conference on Asia South Pacific design automation - ASP-DAC '05  
In this article, we present the first partitioning and placement algorithm for automatic QCA layout. We identify several objectives and constraints that will enhance the buildability of QCA circuits.  ...  Quantum-dot Cellular Automata (QCA) is a novel computing mechanism that can represent binary information based on spatial distribution of an electron charge configuration in chemical molecules.  ...  Wire crossing minimization is critical in QCA placement since QCA layout needs to be done in a single layer, unlike the multilayer CMOS layout.  ... 
doi:10.1145/1120725.1120902 dblp:conf/aspdac/RavichandranNL05 fatcat:crujwfyx6rdo7k37k63kjiqxga

Partitioning and placement for buildable QCA circuits

Sung Kyu Lim, Ramprasad Ravichandran, Mike Niemier
2005 ACM Journal on Emerging Technologies in Computing Systems  
In this article, we present the first partitioning and placement algorithm for automatic QCA layout. We identify several objectives and constraints that will enhance the buildability of QCA circuits.  ...  Quantum-dot Cellular Automata (QCA) is a novel computing mechanism that can represent binary information based on spatial distribution of an electron charge configuration in chemical molecules.  ...  Wire crossing minimization is critical in QCA placement since QCA layout needs to be done in a single layer, unlike the multilayer CMOS layout.  ... 
doi:10.1145/1063803.1063806 fatcat:joj72wiokfge5ojgrgpe5i2xee
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