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Design of low power L2 cache architecture using partial way tag information

A. Divya Jebaseeli, M. Kiruba
2014 2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE)  
In new method, way_tagged cache was used under write-through policy, it's consumed more energy. By maintaining the wag tag of L2 cache in the L1 cache during read operation.  ...  However write through policy incurs large power utilization, while accessing the cache at low level (L2 cache) during write operation.  ...  overhead under the write-through policy.  ... 
doi:10.1109/icgccee.2014.6922292 fatcat:7ko77asvcfgvdehi3kqbigtkyi

A Survey of Emerging Architectural Techniques for Improving Cache Energy Consumption

Washington Bhebhe, Michael Opoku
2016 Communications on Applied Electronics  
A lot of research effort has been put on finding techniques that can improve the energy efficiency of cache architectures.  ...  This work is a survey of energy saving techniques which are grouped on whether they save the dynamic energy, leakage energy or both.  ...  [19] proposed a technique called 'Way-tagged Cache' which is an energy-efficient L2 cache architecture using way-tag information under write-through policy.  ... 
doi:10.5120/cae2016652443 fatcat:hvi6m63qaredfeg3dzecvjws2e

Architectural Techniques for Improving the Power Consumption of NoC-Based CMPs: A Case Study of Cache and Network Layer

Emmanuel Ofori-Attah, Washington Bhebhe, Michael Agyeman
2017 Journal of Low Power Electronics and Applications  
The read architecture can either be a look aside or a look through; whereas the write policy architecture can be a write back or write through.  ...  Connection is established between each node through the routers using links.  ...  [62] proposed a technique called 'Way-tagged Cache', which is an energy-efficient L2 cache architecture using way-tag information under a write-through policy.  ... 
doi:10.3390/jlpea7020014 fatcat:qgf4zaqltfcgpcd525wuio5dwq

Architecting high-performance energy-efficient soft error resilient cache under 3D integration technology

Hongbin Sun, Pengju Ren, Nanning Zheng, Tong Zhang, Tao Li
2011 Microprocessors and microsystems  
Simulation results show that the proposed 3D cache architecture can reduce the power consumption by up to 65% for the L1 instruction cache, 60% for the L1 data cache and 20% for the L2 cache, respectively  ...  However, conventional soft error resilient techniques have significantly increased the access latency and energy consumption in cache memory, thereby resulting in undesirable performance and energy efficiency  ...  We focus on the dynamic energy and access delay while do not estimate the area overhead reduction by removing We assume that reading/writing L2 cache incurs an eight times larger dynamic energy with  ... 
doi:10.1016/j.micpro.2011.01.004 fatcat:gb3qtobfmve23knfosc6n7vkfi

Energy-Efficient Partitioning of Hybrid Caches in Multi-core Architecture [chapter]

Dongwoo Lee, Kiyoung Choi
2015 IFIP Advances in Information and Communication Technology  
The L2 cache is a 16-way set associative cache consisting of 4 ways of SRAM and 12 ways of STT-RAM with asymmetric read/write latency.  ...  Background STT-RAM Technology Spin-Transfer Torque RAM (STT-RAM) is an emerging memory technology, which uses a Magnetic Tunnel Junction (MTJ) as an information carrier.  ... 
doi:10.1007/978-3-319-25279-7_4 fatcat:pzs6ogqx55flde7bcz5xmf5eji

Energy-efficient partitioning of hybrid caches in multi-core architecture

Dongwoo Lee, Kiyoung Choi
2014 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)  
Then a cache miss fills the corresponding block in the SRAM or STT-RAM region based on an existing technique called read-write aware region-based hybrid cache architecture.  ...  Thus, when a store operation from a core causes an L2 cache miss (store miss), the block is assigned to the SRAM cache.  ...  for STT-RAM DRAM DDR3-1333 (10-10-10), 1 channel, 8 banks, 32-entry queue, open-page policy, FR-FCFS policy Table 2 . 2 Energy Consumption of the L2 Cache Read Energy Write Energy Static Power  ... 
doi:10.1109/vlsi-soc.2014.7004174 dblp:conf/vlsi/LeeC14 fatcat:6jp3mzleozbbvcdut4mws4dg54

Designing a practical data filter cache to improve both energy efficiency and performance

Alen Bardizbanyan, Magnus Själander, David Whalley, Per Larsson-Edefors
2013 ACM Transactions on Architecture and Code Optimization (TACO)  
Conventional Data Filter Cache (DFC) designs improve processor energy efficiency, but degrade performance.  ...  Designing a practical data filter cache to improve both energy efficiency and performance. ACM Trans.  ...  Making L1 DC Writes More Efficient All store instructions cause writes to be attempted to both the DFC and the L1 DC, since a write-through policy is used in our design.  ... 
doi:10.1145/2541228.2555310 fatcat:rx5sjuabqfddfmavdeeabsacwe

Designing a practical data filter cache to improve both energy efficiency and performance

Alen Bardizbanyan, Magnus Själander, David Whalley, Per Larsson-Edefors
2013 ACM Transactions on Architecture and Code Optimization (TACO)  
Conventional Data Filter Cache (DFC) designs improve processor energy efficiency, but degrade performance.  ...  Designing a practical data filter cache to improve both energy efficiency and performance. ACM Trans.  ...  Making L1 DC Writes More Efficient All store instructions cause writes to be attempted to both the DFC and the L1 DC, since a write-through policy is used in our design.  ... 
doi:10.1145/2555289.2555310 fatcat:mef2oz6ej5hm5edmdefoyus5ka

Reducing Cache Energy in Embedded Processors Using Early Tag Access and Tag Overflow Buffer

2015 International Journal of Science and Research (IJSR)  
The proposed ETA cache method can be configured under two operation modes to exploit the trade offs between the energy efficiency and performance.  ...  This helps to improve the energy efficiency of data caches in embedded processors.  ...  For L2 caches under the write through policy, a way-tagging technique [2] sends the L2 tag information"s to the L1 cache when the data is loaded from the L2 cache.  ... 
doi:10.21275/v4i12.nov152045 fatcat:pu3qvxyaqzcejnk3zrkpfe6jwy

TRB: Tag Replication Buffer for Enhancing the Reliability of the Cache Tag Array

Shuai Wang, Jie Hu, Sotirios G. Ziavras
2010 2010 IEEE Computer Society Annual Symposium on VLSI  
array in the data cache with low performance, energy and area overheads.  ...  To provide a comprehensive evaluation of the tag-array reliability, we also conduct an architectural vulnerability factor (AVF) analysis for the tag array and propose a refined metric, detected-withoutreplica-AVF  ...  However, if we use a write-through cache, the performance will degrade 3.7% and the energy consumption of the L2 cache will be more than doubled compared to that in a write-back cache as shown in Figure  ... 
doi:10.1109/isvlsi.2010.25 dblp:conf/isvlsi/WangHZ10 fatcat:w7smarf3jbhidb3msiuybnqarq

A new perspective for efficient virtual-cache coherence

Stefanos Kaxiras, Alberto Ros
2013 Proceedings of the 40th Annual International Symposium on Computer Architecture - ISCA '13  
In this context, virtual L1 caches can be used to great advantage, e.g., saving energy consumption by eliminating address translation for hits.  ...  We show that these conditions hold in a new class of simple and efficient request-response protocols that use both selfinvalidation and self-downgrade.This results in a new solution for virtual-cache coherence  ...  Self-downgrade is implemented as a write-through policy.  ... 
doi:10.1145/2485922.2485968 dblp:conf/isca/KaxirasR13 fatcat:rve3vhxsvbhxfogduzo6jrofcu

A new perspective for efficient virtual-cache coherence

Stefanos Kaxiras, Alberto Ros
2013 SIGARCH Computer Architecture News  
In this context, virtual L1 caches can be used to great advantage, e.g., saving energy consumption by eliminating address translation for hits.  ...  We show that these conditions hold in a new class of simple and efficient request-response protocols that use both selfinvalidation and self-downgrade.This results in a new solution for virtual-cache coherence  ...  Self-downgrade is implemented as a write-through policy.  ... 
doi:10.1145/2508148.2485968 fatcat:qxitge7c6beknfh362a72gbltu

High Performance and Energy Efficient Serial Prefetch Architecture [chapter]

Glenn Reinman, Brad Calder, Todd Austin
2002 Lecture Notes in Computer Science  
Energy efficient architecture research has flourished recently, in an attempt to address packaging and cooling concerns of current microprocessor designs, as well as battery life for mobile computers.  ...  Energy is saved by only accessing the correct way of the data component specified by the tag lookup in a previous cycle. The tag component does not stall on a I-cache miss, only the data component.  ...  Acknowledgments We would like to thank Keith Farkas, Norm Jouppi, and the anonymous reviewers for providing useful feedback on this paper.  ... 
doi:10.1007/3-540-47847-7_14 fatcat:vxoheb4yojgnfgxfvlvre74tzu

Building Heterogeneous Unified Virtual Memories (UVMs) without the Overhead

Konstantinos Koukos, Alberto Ros, Erik Hagersten, Stefanos Kaxiras
2016 ACM Transactions on Architecture and Code Optimization (TACO)  
We achieve an average 45% speedup and 45% energy-delay product reduction (20% energy) over the corresponding SC implementation.  ...  The use of HRF simplifies the coherency protocol and the GPU memory management unit (MMU).  ...  grant TIN2012-38341-C04-03, and the "Fundación Seneca-Agencia de Ciencia y Tecnología de la Región de Murcia" under the project "Jóvenes Líderes en Investigación" 18956/JLI/13.  ... 
doi:10.1145/2889488 fatcat:cx5535ifhfgnxe3yocrc6h77sq

Embedded systems to high performance computing using STT-MRAM

Sophiane Senni, Thibaud Delobelle, Odilia Coi, Pierre-Yves Peneau, Lionel Torres, Abdoulaye Gamatie, Pascal Benoit, Gilles Sassatelli
2017 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017  
This paper shows first how STT-MRAM can improve energy efficiency and reliability of future embedded systems.  ...  using multifunctional standardized sTack (MSS)), and the French National Research Agency under grants ANR-15-CE24-0033-01 (MASTA project) and ANR-15-CE25-0007-01 (CONTINUUM project).  ...  ACKNOWLEDGMENT This work has received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement No 687973 -GREAT (heteroGeneous integRated magnetic tEchnology  ... 
doi:10.23919/date.2017.7927046 dblp:conf/date/SenniDCPTGBS17 fatcat:a6gzqipgvjfxji4swhkibb6s44
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