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An emulator network for SIMD machine interconnection networks

S. Diane Smith, H. J. Siegel
<span title="">1979</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/2kokby3zfzen3bd62o6cskolxq" style="color: black;">Proceedings of the 6th annual symposium on Computer architecture - ISCA &#39;79</a> </i> &nbsp;
The emulator network, a single stage interconnection network, can be used to simulate a wide variety of single stage and multistage SIMD interconnection networks.  ...  It is shown how the emulator network can be used to test different network control schemes. Its performance in a partitioned machine environment is discussed.  ...  Section V shows how the emulator network can operate in a machine that is partitioned into smaller SIMD machines, each of size a power of two.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/800090.802913">doi:10.1145/800090.802913</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/isca/SmithS79.html">dblp:conf/isca/SmithS79</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/caxr5wlnajgonph74wf7wuuglq">fatcat:caxr5wlnajgonph74wf7wuuglq</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170812193946/http://www.engr.colostate.edu/~hj/conferences/12.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/79/0a/790ac615f4b2d568c27a01e16bee093bb1b9d061.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/800090.802913"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

Experimental analysis of a mixed-mode parallel architecture using bitonic sequence sorting

Samuel A. Fineberg, Thomas L. Casavant, Howard Jay Siegel
<span title="">1991</span> <i title="Elsevier BV"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/rwjg7tprafhufajayuvxj2q4n4" style="color: black;">Journal of Parallel and Distributed Computing</a> </i> &nbsp;
Finally, a more efficient PE mask generation scheme for multiple "off-the-shelf" microprocessor-based SIMD systems is emulated and its performance is analyzed.  ...  This computation was mapped to both the SIMD and MIMD modes of parallelism, as well as to two hybrids of the SIMD and MIMD modes.  ...  An interconnection network is a set of interconnection functions, each a bijection on the set of PE addresses.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1016/0743-7315(91)90048-e">doi:10.1016/0743-7315(91)90048-e</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/qojxdu2ianh7dmqgq6kfggrmly">fatcat:qojxdu2ianh7dmqgq6kfggrmly</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170808204124/http://www.engr.colostate.edu/~hj/journals/34.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/8c/d4/8cd47d8e2dfeb6233361c3b45124ba80df437509.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1016/0743-7315(91)90048-e"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> elsevier.com </button> </a>

The Queue-Read Queue-Write PRAM Model: Accounting for Contention in Parallel Algorithms

Phillip B. Gibbons, Yossi Matias, Vijaya Ramachandran
<span title="">1998</span> <i title="Society for Industrial &amp; Applied Mathematics (SIAM)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/7dys7zoberdktmxyjciuy5bnse" style="color: black;">SIAM journal on computing (Print)</a> </i> &nbsp;
This matches the bestknown emulation result for the erew pram, and considerably improves upon the best-known efficient emulation for the crcw pram on such networks.  ...  Furthermore, we present a work-preserving emulation of the qrqw pram with only logarithmic slowdown on Valiant's bsp model, and hence on hypercube-type noncombining networks, even when latency, synchronization  ...  This places an upper bound on the number of requests that must be handled by the interconnection network of the parallel machine.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1137/s009753979427491">doi:10.1137/s009753979427491</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/bwua22baujghvesgxzawx5ky2q">fatcat:bwua22baujghvesgxzawx5ky2q</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20070824131506/http://www.pittsburgh.intel-research.net/people/gibbons/papers/qrqw-sicomp.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/53/0a/530adda2d05a3b248db6f0e3fc610ea0603ed2fb.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1137/s009753979427491"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> Publisher / doi.org </button> </a>

PIMCaffe: Functional Evaluation of a Machine Learning Framework for In-Memory Neural Processing Unit

Won Jeon, Jiwon Lee, Dongseok Kang, Hongju Kal, Won Woo Ro
<span title="">2021</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/q7qi7j4ckfac7ehf3mjbso4hne" style="color: black;">IEEE Access</a> </i> &nbsp;
In an VOLUME 9, 2021 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/  ...  On the other hand, for voice processing tasks, Recurrent Neural Networks (RNNs) show superior performance compared to conventional approaches.  ...  MACHINE LEARNING FRAMEWORK FOR FPGA For deep learning applications, the neural network model must vary based on the purpose of the application and target execution environment.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/access.2021.3094043">doi:10.1109/access.2021.3094043</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/xacvcg7dyjfs5dtugku2fimrem">fatcat:xacvcg7dyjfs5dtugku2fimrem</a> </span>
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Using emulations to enhance the performance of parallel architectures

B. Obrenic, M.C. Herbordt, A.L. Rosenberg, C.C. Weems
<span title="">1999</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/ll6bfs5o6bahfinh3u5z2cnyoy" style="color: black;">IEEE Transactions on Parallel and Distributed Systems</a> </i> &nbsp;
virtual machine f k that has: 1) a datapath and memory bus whose emulated width is k bits, as opposed to e's 1-bit width and 2) an instruction set that operates on k-bit words, in contrast to e's instruction  ...  The vehicle for this demonstration is a suite of algorithms that endow an N-processor bit-serial processor array e with a ªmeta-instructionº GAUGE k, which (logically) reconfigures e into an N=k-processor  ...  A preliminary version of this paper entitled ªAchieving Multigauge Behavior in SIMD Architectures via Emulation,º pp. [186][187][188][189][190][191][192][193][194][195], was presented at the Proc.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/71.808155">doi:10.1109/71.808155</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/ywjp6sqk5jai7cswtp7gc7xezq">fatcat:ywjp6sqk5jai7cswtp7gc7xezq</a> </span>
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Interconnection Networks Using Shuffles

P.-Y. Chen, D.H. Lawrie, P.-C. Yew, D.A. Padua
<span title="">1981</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/dsrvu6bllzai7oj3hktnc5yf4q" style="color: black;">Computer</a> </i> &nbsp;
of the results dealing with interconnection networks for SIMD and MIMD computers.  ...  SIMD applications Single-stage networks (those that are mesh connected and shuffle connected) were among the first to be used for SIMD machines, 1,20-22 and they are still popular because of their low  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/c-m.1981.220297">doi:10.1109/c-m.1981.220297</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/fqwivvuws5g6thqiv7vciljwoy">fatcat:fqwivvuws5g6thqiv7vciljwoy</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170818134841/https://www.computer.org/csdl/mags/co/1981/12/01667204.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/a5/e3/a5e33f42759acc180778dde3eb8fd5d8551e2274.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/c-m.1981.220297"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Page 5689 of Mathematical Reviews Vol. , Issue 89J [page]

<span title="">1989</span> <i title="American Mathematical Society"> <a target="_blank" rel="noopener" href="https://archive.org/details/pub_mathematical-reviews" style="color: black;">Mathematical Reviews </a> </i> &nbsp;
for a network of processors (SIMD- or MIMD-machines).  ...  Finally, an analysis of algorithms for deadlock-free packet switching networks with variable packet size is analyzed.  ... 
<span class="external-identifiers"> </span>
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Using FPGAs to implement a reconfigurable highly parallel computer [chapter]

Arne Linde, Tomas Nordström, Mikael Taveniku
<span title="">1993</span> <i title="Springer Berlin Heidelberg"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/2w3awgokqne6te4nvlofavy5a4" style="color: black;">Lecture Notes in Computer Science</a> </i> &nbsp;
To get efficient usage and high performance with the FPGA circuits signal flow plays an important role.  ...  In the primary application area, which is artificial neural networks, the gains of extensions like bit-serial multipliers or counters can quickly be found.  ...  The chip consists of a number of combinatorial logic blocks (CLB), some input-output blocks (IOB) and an interconnection network (ICN).  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/3-540-57091-8_45">doi:10.1007/3-540-57091-8_45</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/dnzf3jrnmjhbxngep73b7vfb7a">fatcat:dnzf3jrnmjhbxngep73b7vfb7a</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170705124028/http://www.nordstrom.nu/tomas/publications/LinEtAt_1992_FPL.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/04/ed/04ed43aecc576cb1dd8187b4449441355ac2eec6.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/3-540-57091-8_45"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> springer.com </button> </a>

Computer Architecture with Associative Processor Replacing Last-Level Cache and SIMD Accelerator

Leonid Yavits, Amir Morad, Ran Ginosar
<span title="">2015</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/5jlmyrayyrdazh5awdlsoec77q" style="color: black;">IEEE transactions on computers</a> </i> &nbsp;
This study presents a computer architecture where a last level cache and a SIMD accelerator are replaced by an Associative Processor.  ...  Comparative analysis supported by cycle-accurate simulation and emulation shows that this architecture may outperform a conventional computer architecture comprising a SIMD coprocessor and a shared last  ...  ACKNOWLEDGMENT This research was partially funded by the Intel Collaborative Research Institute for Computational Intelligence and by Hasso-Plattner-Institut.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tc.2013.220">doi:10.1109/tc.2013.220</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/fbep2ik5hrcwvowxrzml6mddsm">fatcat:fbep2ik5hrcwvowxrzml6mddsm</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170829015555/http://webee.technion.ac.il/people/ran/papers/YavitsAssociative.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/1e/4d/1e4d081c6fa2103ccd0b9d977d98dffaff3a6f3c.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tc.2013.220"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

The Rewrite Rule Machine node architecture and its performance [chapter]

Patrick Lincoln, José Meseguer, Livio Ricciulli
<span title="">1994</span> <i title="Springer Berlin Heidelberg"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/2w3awgokqne6te4nvlofavy5a4" style="color: black;">Lecture Notes in Computer Science</a> </i> &nbsp;
The RRM's node architecture consists of a SIMD processor, a SIMD controller, local memory, and network and I/O interfaces.  ...  In a parallel machine this is implemented by communication on a network, on which messages travel to reach their destination objects.  ...  Joseph Goguen for his fundamental contributions to the RRM and for his most valuable assistance and advice, and Prof. Hitoshi Aida for his crucial help in earlier stages of the RRM design.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/3-540-58430-7_45">doi:10.1007/3-540-58430-7_45</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/btpgwvpicngxfbpzks7dxpyhvm">fatcat:btpgwvpicngxfbpzks7dxpyhvm</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20161214140238/http://www.csl.sri.com/papers/conpar94/conpar94.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/a9/39/a9395e0a7401748ef27d7ff685a658178a06e032.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/3-540-58430-7_45"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> springer.com </button> </a>

Aspen: A domain specific language for performance modeling

Kyle L. Spafford, Jeffrey S. Vetter
<span title="">2012</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/zigbcra6rjdivda6lkzknwuo5q" style="color: black;">2012 International Conference for High Performance Computing, Networking, Storage and Analysis</a> </i> &nbsp;
It includes a formal specification of an application's performance behavior and an abstract machine model.  ...  We provide an overview of Aspen's features and demonstrate how it can be used to express a performance model for a three dimensional Fast Fourier Transform.  ...  Government retains a non-exclusive, royalty-free license to publish or reproduce the published form of this contribution, or allow others to do so, for U.S. Government purposes.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/sc.2012.20">doi:10.1109/sc.2012.20</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/sc/SpaffordV12.html">dblp:conf/sc/SpaffordV12</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/mp6zghtd7rgdlcmmjt2ahfytr4">fatcat:mp6zghtd7rgdlcmmjt2ahfytr4</a> </span>
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A data parallel implementation of the TRFD program from the Perfect benchmarks [chapter]

David J. Lilja, Jonathan Schmitt
<span title="">1994</span> <i title="Elsevier"> Massively Parallel Processing Applications and Development </i> &nbsp;
We find that this program maps well to an SIMD architecture when the underlying structure of the algorithm is understood.  ...  We describe our experiences porting the trfd program from this collection to the Connection Machine CM-200 and CM-5.  ...  Thanks also to Steve VanderWiel for his comments and to Dawn Sweno for her assistance in gathering some of the CM-5 data.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1016/b978-0-444-81784-6.50046-4">doi:10.1016/b978-0-444-81784-6.50046-4</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/beptyrswvbadrec3luwvtxw7l4">fatcat:beptyrswvbadrec3luwvtxw7l4</a> </span>
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An FPGA Implementation of a Distributed Virtual Machine [chapter]

Lee A. Jensen, Lance R. Williams
<span title="">2018</span> <i title="Springer International Publishing"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/2w3awgokqne6te4nvlofavy5a4" style="color: black;">Lecture Notes in Computer Science</a> </i> &nbsp;
This was accomplished by compiling a VHDL specification of a special purpose distributed memory multicomputer with a mesh interconnection network into a globally asynchronous, locally synchronous (GALS  ...  ) circuit in an FPGA.  ...  interconnection network.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/978-3-319-92435-9_8">doi:10.1007/978-3-319-92435-9_8</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/dtkxp2mgezbzdaj4qqqq64xl2u">fatcat:dtkxp2mgezbzdaj4qqqq64xl2u</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20190225093011/http://pdfs.semanticscholar.org/6080/8eedc25a63a3f7014770edd359ea09c51c33.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/60/80/60808eedc25a63a3f7014770edd359ea09c51c33.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/978-3-319-92435-9_8"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> springer.com </button> </a>

Teaching tools for parallel processing

Emina Milovanovic, Natalija Stojanovic
<span title="">2005</span> <i title="National Library of Serbia"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/i5izkhv2lvg4blwkmbvmyjratu" style="color: black;">Facta universitatis - series Electronics and Energetics</a> </i> &nbsp;
to treat a network of workstations as a message passing MIMD multicomputer with distributed memory.  ...  Parallaxis is a sophisticated SIMD simulator which runs on a variety of platforms.jBACI shared memory simulator supports the MIMD model of computing with a common shared memory.PVM and MPI allow students  ...  PVM and MPI PVM is an integrated set of software tools and libraries that emulates a generalpurpose, flexible, heterogeneous concurrent computing framework on interconnected computers of varied architecture  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.2298/fuee0502219m">doi:10.2298/fuee0502219m</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/2i5j75dgsfa2xjny6lwkp2fu2i">fatcat:2i5j75dgsfa2xjny6lwkp2fu2i</a> </span>
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Project Triton: Towards Improved Programmability of Parallel Computers [chapter]

Michael Philippsen, Thomas M. Warschko, Walter F. Tichy, Christian G. Herter, Ernst A. Heinz, Paul Lukowicz
<span title="">1994</span> <i title="Springer US"> The Interaction of Compilation Technology and Computer Architecture </i> &nbsp;
Triton/1 is a scalable mixed-mode SIMD/MIMD parallel computer with a highly e cient communications network.  ...  We present t e c hniques for the e cient translation of Modula-2* and similar imperative languages for several modern parallel machines and derive recommendations for future parallel architectures.  ...  , and Markus Mock for many v aluable ideas and their implementation work.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/978-1-4615-2684-1_10">doi:10.1007/978-1-4615-2684-1_10</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/dwspumwicjcmdgqcy5a5dcnaze">fatcat:dwspumwicjcmdgqcy5a5dcnaze</a> </span>
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