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An embedded reconfigurable SIMD DSP with capability of dimension-controllable vector processing

Liang Han, Jie Chen, Chaoxian Zhou, Ying Li, Xin Zhang, Zhibi Liu, Xiaoyun Wei, Baofeng Li
IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings.  
The SIMD scheme is extended with the instant-scalability of datapaths (ISSIMD), which offers the DSP a capability of dimension-controllable vector processing, so that to provide flexibility for different  ...  Equipped with eight SIMD-controlled 16-bit datapaths which can also be reconfigured as two 32-bit datapaths, the DSP core can process both 16-bit and 32-bit data in parallel, showing high performance,  ...  The SIMD-controlled datapath array enhanced with instant-scalability supplies the DSP with a capability of dimension-controllable vector processing.  ... 
doi:10.1109/iccd.2004.1347960 dblp:conf/iccd/HanCZLZLWL04 fatcat:j2hv45rms5bfvjqwwkzopdha2i

Exploiting mixed-mode parallelism for matrix operations on the HERA architecture through reconfiguration

X. Wang, S.G. Ziavras
2006 IEE Proceedings - Computers and digital Techniques  
Each processing element (PE) is centered on a single-precision IEEE 754 FPU with tightly-coupled local memory, and supports dynamic switching between SIMD and MIMD at runtime.  ...  In these systems, the processors serving as control units and the computing PEs were most often exclusively defined at static time and there was an interconnection  ...  Introduction With the recent achievement of multi-million-gate platform FPGAs to contain richer embedded feature sets, such as plenty of on-chip memory, DSP blocks and embedded microprocessor IP cores,  ... 
doi:10.1049/ip-cdt:20045136 fatcat:vj5iz7y3mvhlld2apirlqna54u

A HW/SW design methodology for embedded SIMD vector signal processors

J.P. Robelly, G. Cichon, H. Ahlendorf, G. Fettweis
2008 International Journal of Embedded Systems  
models of DSP cores with a scalable level of SIMD parallelism.  ...  SIMD processors have made their way from supercomputers architectures through embedded real-time signal processing.  ...  ACKNOWLEDGMENT We would like to thank the people of the CATS research group at the Technische Universitaet Dresden, from which we are honored to be members.  ... 
doi:10.1504/ijes.2008.020297 fatcat:crlh74ypxbgtvaxdxku23lrbla

The Sandbridge SB3011 Platform

John Glossner, Daniel Iancu, Mayan Moudgill, Gary Nacer, Sanjay Jinturkar, Stuart Stanley, Michael Schulte
2007 EURASIP Journal on Embedded Systems  
We describe the software development system that enables real-time execution of communications and multimedia applications.  ...  We provide results for a number of interesting communications and multimedia systems including UMTS, DVB-H, WiMAX, WiFi, and NTSC video decoding.  ...  Each DSP is capable of issuing multiple operations per cycle including data parallel vector operations.  ... 
doi:10.1186/1687-3963-2007-056467 fatcat:uuo67bgefzetpdlm6246mkjdja

The Sandbridge SB3011 Platform

John Glossner, Daniel Iancu, Mayan Moudgill, Gary Nacer, Sanjay Jinturkar, Stuart Stanley, Michael Schulte
2007 EURASIP Journal on Embedded Systems  
We describe the software development system that enables real-time execution of communications and multimedia applications.  ...  We provide results for a number of interesting communications and multimedia systems including UMTS, DVB-H, WiMAX, WiFi, and NTSC video decoding.  ...  Each DSP is capable of issuing multiple operations per cycle including data parallel vector operations.  ... 
doi:10.1155/2007/56467 fatcat:gicryhrnojgjngvd35vfkmhrhe

A Survey on Coarse-Grained Reconfigurable Architectures from a Performance Perspective [article]

Artur Podobas, Kentaro Sano, Satoshi Matsuoka
2020 arXiv   pre-print
Among the more salient and practical of the post-Moore alternatives are reconfigurable systems, with Coarse-Grained Reconfigurable Architectures (CGRAs) seemingly capable of striking a balance between  ...  With the end of both Dennard's scaling and Moore's law, computer users and researchers are aggressively exploring alternative forms of compute in order to continue the performance scaling that we have  ...  RaPiD [40] , [41] is an CGRA that arranged its reconfigurable processing elements in a single dimension.  ... 
arXiv:2004.04509v1 fatcat:sxnq32chxjf6hfc5ygjsxqjwl4

A Survey on Coarse-Grained Reconfigurable Architectures from a Performance Perspective

Artur Podobas, Kentaro Sano, Satoshi Matsuoka
2020 IEEE Access  
Among the more salient and practical of the post-Moore alternatives are reconfigurable systems, with Coarse-Grained Reconfigurable Architectures (CGRAs) seemingly capable of striking a balance between  ...  ., [15]-[17]), and have driven forth a different branch of reconfigurable architecture: the Coarse-Grained Reconfigurable Architecture (CGRAs).  ...  SIMD RA focuses on embedding support to modularize the CGRA-array to supporting multiple discrete controllable regions that (may) operate in SIMD fashion.  ... 
doi:10.1109/access.2020.3012084 fatcat:xx6k4lxbjbc4tjebbymp42w634

Flexible and High Performance ASIPs for Pixel Level Image Processing and Two Dimensional Image Processing

Hsuan-Chun Liao, Mochamad Asri, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda
2013 Journal of Information Processing  
PXL ASIP, which has a reconfigurable multi bank memory module and an SIMD type computation pipeline, is designed for pixel level image processing, while 2D ASIP, which has slide register module and reconfigurable  ...  Processing during capture and display are non-standard and vary from case by case, hence, the flexibility of image processing engines has turned out to be an important issue.  ...  The design concept of PXL ASIP is to support a wider range of pixel level image processing with reconfigurable multi bank memory module and SIMD type computation modules.  ... 
doi:10.2197/ipsjjip.21.552 fatcat:rrisikueqja57aa327zf6us3sm

Prototyping Embedded Dsp Systems - From Specification To Implementation

Zoran Salcic
2004 Zenodo  
Publication in the conference proceedings of EUSIPCO, Viena, Austria, 2004  ...  of embedded DSP systems and generally can be viewed as new kind of reconfigurable hybrid architectures [13] .  ...  INTRODUCTION Digital signal processing (DSP) algorithms are used in ever increasing number of embedded real-time applications that include systems as simple as consumer products to very sophisticated control  ... 
doi:10.5281/zenodo.38706 fatcat:navkxtet35ae7hpjep3xrbe6oi

Towards future adaptive multiprocessor systems-on-chip: An innovative approach for flexible architectures

Fabrice Lemonnier, Philippe Millet, Gabriel Marchesan Almeida, Michael Hubner, Jurgen Becker, Sebastien Pillement, Olivier Sentieys, Martijn Koedam, Shubhendu Sinha, Kees Goossens, Christian Piguet, Marc-Nicolas Morgan (+1 others)
2012 2012 International Conference on Embedded Computer Systems (SAMOS)  
The different components are based on low power DSP cores and an eFPGA on which dedicated IPs can be dynamically configured at run-time.  ...  This is associated with self adaptive strategies endowed by an operating system kernel that provides a set of functions that guarantee quality of service (QoS) by implementing runtime adaptive policies  ...  It contains a scalable vector processing unit (VPU) organized in "slices" containing registers and data processing elements which are used by single instruction multiple data (SIMD) vector operations.  ... 
doi:10.1109/samos.2012.6404179 dblp:conf/samos/LemonnierMAHBPSKSGPML12 fatcat:vvdjjie7xzaarjn44536hcx6ny

Compiling Scilab to high performance embedded multicore systems

Timo Stripf, Oliver Oey, Thomas Bruckschloegl, Juergen Becker, Gerard Rauwerda, Kim Sunesen, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Steven Derrien, Olivier Sentieys, Nikolaos Kavvadias (+5 others)
2013 Microprocessors and microsystems  
The mapping process of high performance embedded applications to today's multiprocessor system-onchip devices suffers from a complex toolchain and programming process.  ...  The problem is the expression of parallelism with a pure imperative programming language, which is commonly C.  ...  floating-point SIMD capabilities.  ... 
doi:10.1016/j.micpro.2013.07.004 fatcat:pdh6kpwp25galdrdtvpv45l2cy

Towards the Optimal Hardware Architecture for Computer Vision [chapter]

Alejandro Nieto, David Lpez, Vctor Brea
2012 Machine Vision - Applications and Systems  
SIMD SIMD (Single Instruction Multiple Data) computers have an unique control unit and multiple processing units.  ...  This is specially relevant in embedded applications, to take advantage of the multi-core capabilities of modern DSPs.  ... 
doi:10.5772/34023 fatcat:higcvn5ffrhzlieberxwiatasa

Exploiting Fine-Grain Ordered Parallelism in Dense Matrix Algorithms [article]

Jian Weng, Vidushi Dadu, Tony Nowatzki
2019 arXiv   pre-print
Because CPUs and DSPs lose order-of-magnitude performance/hardware utilization, costly and inflexible ASICs are often employed in signal processing pipelines.  ...  It supports the above features in its ISA and microarchitecture, and further uses a novel vector-stream control paradigm to reduce control overheads.  ...  Short-vector SIMD is one way to reduce control overhead; one SIMD instruction expresses multiple operations over a fixed number of data items.  ... 
arXiv:1905.06238v1 fatcat:6iuqxbtwwrevxju27gyh5mlikq

Signal Processing with Teams of Embedded Workhorse Processors

R. F. Hobson, A. R. Dyck, K. L. Cheung, B. Ressl
2006 EURASIP Journal on Embedded Systems  
This paper describes an architecture based on clusters of embedded "workhorse" processors which can be dynamically harnessed in real time to support a wide range of computational tasks.  ...  Due to the complexity and continuing evolution of such systems, it is desirable to maintain as much software controllability in the field as possible.  ...  The majority of processing cycles for this application (and WCDMA rake and search processing) are consumed by 2-dimensional (2D) correlations. The first dimension (horizontal, cf.  ... 
doi:10.1155/es/2006/69484 fatcat:h7vnrr4f4jdbrep4cawranr2kq

Signal Processing with Teams of Embedded Workhorse Processors

RF Hobson, AR Dyck, KL Cheung, B Ressl
2006 EURASIP Journal on Embedded Systems  
This paper describes an architecture based on clusters of embedded "workhorse" processors which can be dynamically harnessed in real time to support a wide range of computational tasks.  ...  Due to the complexity and continuing evolution of such systems, it is desirable to maintain as much software controllability in the field as possible.  ...  The majority of processing cycles for this application (and WCDMA rake and search processing) are consumed by 2-dimensional (2D) correlations. The first dimension (horizontal, cf.  ... 
doi:10.1186/1687-3963-2006-069484 fatcat:lr5xadoaanfrrcgg5adxow5fqm
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