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An On-Chip AHB Bus Tracer With Real-Time Compression and Dynamic Multiresolution Supports for SoC

Fu-Ching Yang, Yi-Ting Lin, Chung-Fu Kao, Ing-Jer Huang
2011 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
On the other hand, SYS-HMRBT supports tracing after/before an event triggering, named post-triggering trace/pre-triggering trace, respectively.  ...  As a case study, it has been integrated into a 3-D graphics SoC to facilitate the debugging and monitoring of the system behaviors.  ...  As for the multi-resolution support, HTM and AMBA Navigator have limited abstraction capability in the timing dimension. They filter signals when the bus state is in the IDLE or BUSY cycles.  ... 
doi:10.1109/tvlsi.2009.2039811 fatcat:bhm2tw2z4jhuhddgqlibn42xgi

MPARM: Exploring the Multi-Processor SoC Design Space with SystemC

Luca Benini, Davide Bertozzi, Alessandro Bogliolo, Francesco Menichelli, Mauro Olivieri
2005 Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology  
We developed a complete simulation platform for a MP-SoC called MP-ARM, based on SystemC as modelling and simulation environment, and including models for processors, the AMBA bus compliant communication  ...  These multi-processor systems-on-chip (MP-SoC) can provide a high degree of flexibility and represent the most efficient architectural solution for supporting multimedia applications, characterized by  ...  AMBA Bus Model AMBA is a widely used standard defining the communication architecture for high performance embedded systems [19] .  ... 
doi:10.1007/s11265-005-6648-1 fatcat:atufrbrdxjcb7pmiad7fuqwbky

Manycore simulation for peta-scale system design: Motivation, tools, challenges and prospects

Javad Zarrin, Rui L. Aguiar, João Paulo Barraca
2017 Simulation modelling practice and theory  
Abstract The architecture design of peta-scale computing systems is complex and presents lots of difficulties to designs, as current tools lack support for relevant features of future scenarios.  ...  In this paper, we present the challenges for simulating future large scale manycore environments, and we investigate the adequacy of current modeling and simulation tools, methodologies and techniques.  ...  However, they might fail to adequately support embedded software (in terms of writing or debugging), which is an important requirement for SoC design [129] , are often slow compared to the traditional  ... 
doi:10.1016/j.simpat.2016.12.014 fatcat:j2acoyv235awfjkz6w7krvzh44

CONTREX: Design of Embedded Mixed-Criticality CONTRol Systems under Consideration of EXtra-Functional Properties

Ralph Gorgen, Kim Gruttner, Fernando Herrera, Pablo Penil, Julio Medina, Eugenio Villar, Gianluca Palermo, William Fornaciari, Carlo Brandolese, Davide Gadioli, Sara Bocchio, Luca Ceva (+10 others)
2016 2016 Euromicro Conference on Digital System Design (DSD)  
The M2M Integration platform is based on two main components: an embedded pervasive framework (Kura) and a Cloud platform.  ...  Section 2.1.6 proposes our new multi-core SoC based avionic that overcomes the limitations following the idea of integrating all control functions of different criticalities to one high performance MPSoC  ...  At all levels, but especially for in-field devices, power consumption is a critical issue.  ... 
doi:10.1109/dsd.2016.95 dblp:conf/dsd/GorgenGHPMVPFBG16 fatcat:t4f6yfdmrnfwfozoj2iveywwna

Addressing computational and networking constraints to enable video streaming from wireless appliances

S. Chandra, S. Dey
2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005.  
In this work, we use an in-house cycleaccurate system simulator [45] with integrated power models to obtain dynamic and leakage power traces for each SoC component.  ...  More re- cently, multi-frequency, multi-voltage SoC design style has caught attention of many researchers [66].  ...  Voltage-delay characteristics To take into account process variations, we compute the required voltage for the required delay of a given chip instance using the delay information of the instance at a known  ... 
doi:10.1109/estmed.2005.1518064 dblp:conf/estimedia/ChandraD05 fatcat:3kjqqg4gkvaj7gnganjbm6q4pe

A General Approach to High-Level Energy and Performance Estimation in System-on-Chip Architectures

Sandro Penolazzi, Ahmed Hemani, Luca Bolognino
2009 Journal of Low Power Electronics  
for the Leon3 processor was first created and a multi-core NoC-based SoC, which from now on will be called McNoC.  ...  MILAN [47] , [49] stands for Model-based Integrated simuLAtioN.  ...  In case that an application takes different branches depending on the value received, the Funtime user chooses the values according to the specific needs, so to have a trace of primary transactions available  ... 
doi:10.1166/jolpe.2009.1037 fatcat:rcs4t4wctvaw3pkhsdjp4fnvsm

Design and Verification Environment for High-Performance Video-Based Embedded Systems [chapter]

Michael Mefenza, Franck Yonga, Christophe Bobda
2014 Distributed Embedded Smart Cameras  
Starting with an executable specification in OpenCV, we provide subsequent refinements and verification down to a system-on-chip prototype into an FPGA-Based smart camera.  ...  In this dissertation, a method and a tool to enable design and verification of computation demanding embedded vision-based systems is presented.  ...  The Xilinx Zynq Base TRD from [26] is an embedded video processing application designed to showcase various features and capabilities of the Zynq Z-7020 AP SoC device for the embedded domain.  ... 
doi:10.1007/978-1-4614-7705-1_4 fatcat:wx73qh32mrekfg2poxusgkfwya

Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research Studies

Prateek Shantharama, Akhilesh S. Thyagaturu, Martin Reisslein
2020 IEEE Access  
Hardware based systems are driven by an embedded software (firmware, microcode), with microprocessor, microcontroller, Digital Signal Processor (DSP), or Application-Specific Integrated Circuit (ASIC)  ...  (AMBA) [149].  ... 
doi:10.1109/access.2020.3008250 fatcat:kv4znpypqbatfk2m3lpzvzb2nu

Rhealstone Benchmarking of FreeRTOS and the Xilinx Zynq Extensible Processing Platform [article]

(:Unkn) Unknown, University, My, Dennis Silage
(PL) which provide the requisite capabilities for the increasing demands of embedded processing applications.  ...  Embedded system designers require deterministic, real-time operating system (RTOS) support for the commonly available processing hardware.  ...  CoreSight is an on-chip debug and real-time trace kit for SoC designs utilizing ARM processors to optimize debugging the system. [20] The Cortex A-9 MPCore with 2 cores integrated as hard IP component  ... 
doi:10.34944/dspace/807 fatcat:akw7pn7xjfbkhgmyjnuzka5fau

Design and Optimization of Networks-on-Chip for Future Heterogeneous Systems-on-Chip

Young Jin Yoon
Thus, I propose FINDNOC, an integrated framework for the generation, optimization, and validation of NoCs for future heterogeneous SoCs.  ...  Second, they do not provide an integrated environment for software-hardware co-development.  ...  Related Work While bus-based AMBA AHB protocol [11] .  ... 
doi:10.7916/d8vm4j04 fatcat:hmpghmxihzfc5hjnrskoyz6doi

Scalable System-on-Chip Design

Paolo Mantovani
The rise of SoCs corresponds to a rapid decrease of the opportunity cost for integrating accelerators.  ...  This paradigm shift defined the concept of {\em system-on-chip} (SoC) as a single-chip design that integrates several heterogeneous components.  ...  This trend is visible across many classes of integrated circuits, from server processors to SoCs for embedded applications.  ... 
doi:10.7916/d8ws95mk fatcat:egzvpahukvc43ccz7ge66afyze

Tecniche di progettazione tollerante alle variazioni per circuiti digitali in tecnologie nanometriche

Giacomo <1979> Paci, Luca Benini
The ITRS roadmap suggests the following research steps to integrate the design for manufacturability and reliability in the standard CAD automated design flow: i) The implementation of new analysis algorithms  ...  Consequently the deep sub-micron devices will require solutions which will imply several design levels, as system and logic, and new approaches called Design For Manufacturability (DFM) and Design For  ...  The tool was used to analyze the impact of self-timed asynchronous logic stages in an embedded microprocessor.  ... 
doi:10.6092/unibo/amsdottorato/1497 fatcat:i3e6x47ymvha7gpgssuycumb4q

MEMTRACE: A Memory, Performance and Energy Profiler Targeting RISC-Based Embedded Systems for Data-Intensive Applications [article]

Heiko Hübert, Technische Universität Berlin, Technische Universität Berlin, Hans-Ulrich Post
Memory and energy profiling for embedded systems have become major issues within the last 10 years.  ...  Results are based on generic processor architectures or taken with a low sample rate, or the tools apply source code instrumentation.  ...  My work within the Embedded System Group (ESG) of the Image Processing Department laid the foundations and provided inspiration for this dissertation.  ... 
doi:10.14279/depositonce-2175 fatcat:p6ksds3hhrhczdq4na2qutxc4q

Interconnection systems for highly integrated computation devices

Federico <1978> Angiolini, Luca Benini
The resulting outcome, especially in the embedded domain, has often been called SYSTEM-ON-CHIP (SOC) or MULTI-PROCESSOR SYSTEM-ON-CHIP (MPSOC).  ...  The sustained demand for faster,more powerful chips has beenmet by the availability of chip manufacturing processes allowing for the integration of increasing numbers of computation units onto a single  ...  An actual 130nm case study layout obtained from an industrial tool March 13, 2008 Federico Angiolini 142 (Cadence SoC Encounter [217] ) of a 30-core multi-media SoC with the NoC designed using our methodology  ... 
doi:10.6092/unibo/amsdottorato/931 fatcat:d6uz2egvvfd4lgjwvnadzjjdra

Mapping and management of communication services on MP-SoC platforms [article]

Marescaux, TM (Théodore), Corporaal, H (Henk), Verkest, DTML (Diederik)
Many state-of-the art SoCs use multi-layer system buses such as the ST-Bus or the multi-layer AMBA (Section 3.5).  ...  It is thus well adapted for usage on an embedded processor.  ...  For embedded MP-SoC application mapping we attempt figures for timing or energy consumption of certain components are input to the simulator as an XML file ( Figure B .1).  ... 
doi:10.6100/ir629360 fatcat:e5kz6vvr7fguldjhdpjyge3u34
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