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An Efficient Implementation of LZW Decompression in the FPGA

Xin Zhou, Yasuaki Ito, Koji Nakano
2016 2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)  
Since the proposed hardware implementation of LZW compression is compactly designed, we have succeeded in implementing 24 identical circuits in an FPGA, where the clock frequency of FPGA is 163.35MHz.  ...  In the proposed architecture, we efficiently use dual-port block RAMs embedded in the FPGA to implement a hash table that is used as a dictionary.  ...  The main goal of this paper is to develop an efficient hardware architecture of LZW compression and implement it in an FPGA (Field Programmable Gate Array).  ... 
doi:10.1109/ipdpsw.2016.33 dblp:conf/ipps/ZhouIN16 fatcat:3xgy5blcerhdjlkgnwfmxowdwe

Compression and Encryption of Vital Signals Using an SoC-FPGA

Carlos Andres Gómez García, Jaime Velasco Medina
2021 Dyna  
In this case, WolfSSL library is used for the implementation of the Transport Layer Security (TLS) protocol, whose encryption function is accelerated by the AES processor designed on a System on Chip -  ...  A multiparameter board and an SoC-FPGA development board make up the vital signs measurement system, which was calibrated and verified by a commercial patient simulator.  ...  Flow diagram of (a) LZW compression, and (b) LZW decompression algorithms.  ... 
doi:10.15446/dyna.v88n219.92532 fatcat:7gidujdxqbfstpo43bhdjbfnna


Ivan Mozghovyi, Anatoliy Sergiyenko, Roman Yershov
2021 Information, Computing and Intelligent systems  
It has led to a decrease in lookup time and an increase in the speed of data compression, and in turn, allows developing the method of constructing a hardware compression accelerator during the future  ...  This paper is devoted to the compression of GIF images, using a modified LZW algorithm with a tree-based dictionary.  ...  The authors of the paper [9] propose an FPGA-based implementation of the LZW algorithm.  ... 
doi:10.20535/2708-4930.2.2021.244189 fatcat:wrvbotbmw5gbfes3hlj5uzzrwu

Resource-constrained FPGA/DNN co-design

Zhichao Zhang, Abbas Z. Kouzani
2021 Neural computing & applications (Print)  
Next, a DNN overlay is developed, combining the decompression of the DNN parameters and DNN inference, to allow the execution of the DNN on a FPGA on the PYNQ-Z2 board.  ...  In this paper, a DNN model is used for the analysis of the data captured using an electrochemical method to determine the concentration of a neurotransmitter and the recoding electrode.  ...  Acknowledgements The authors would like to thank Dr. Yoonbae Oh and Dr. Kevin E. Bennet of Mayo Clinic for providing the FSCV dataset used.  ... 
doi:10.1007/s00521-021-06113-4 pmid:34025038 pmcid:PMC8122185 fatcat:7e7nkthbxja4lpdyozxfjyht3a

Bitstream compression techniques for Virtex 4 FPGAs

Radu Stefan, Sorin D. Cotofana
2008 2008 International Conference on Field Programmable Logic and Applications  
We evaluate the efficiency of the proposed methods along with state of the art compression algorithms on a number of benchmark circuits, some selected from the available open source implementations and  ...  All our implemented decompressors are shown to use less than 1.5% of the slices available on the FPGA device.  ...  However, the FPGAs in the Virtex 4 family [7] are capable of decompressing the bitstream internally, with a decompressor implemented on the actual FPGA fabric, as indicated in studies of Huebner [8]  ... 
doi:10.1109/fpl.2008.4629952 dblp:conf/fpl/StefanC08 fatcat:wr5xpq23ajbmvk7pj4cbdmgys4

Data Compression Device Based on Modified LZ4 Algorithm

Weiqiang Liu, Faqiang Mei, Chenghua Wang, Maire O'Neill, Earl E. Swartzlander
2018 IEEE transactions on consumer electronics  
CONCLUSION This paper presents a modified LZ4 algorithm and its FPGA implementations. Several aspects of the original LZ4 algorithm are modified for efficient hardware implementation.  ...  The implementation results on an FPGA platform show the proposed MLZ4 architecture provides the highest throughput performance compared with previous FPGA implementations of LZ algorithms, which makes  ...  In addition, he has served as an associate editor for  ... 
doi:10.1109/tce.2018.2810480 fatcat:q6qidflai5a53eiauc333g4c2q

ZDC: A Zone Data Compression Method for Solid State Drive Based Flash Memory

Xin Ye, Zhengjun Zhai, Xiaochang Li
2020 Symmetry  
At present, the main problem facing data compression of SSD is how to improve the efficiency of data compression and decompression.  ...  In order to improve the performance of data compression and decompression, this study proposes a method of SSD data deduplication based on zone division.  ...  Through the address mapping function in FTL, the zone division of NAND Flash memory space is realized. The specific division is introduced in Section 2.3. The FPGA mainly implements data compression.  ... 
doi:10.3390/sym12040623 fatcat:kv4yc436lfgl5o5nbmpxwzk74i

Layered Lossless Compression Method of Massive Fault Recording Data

Jinhong Di, Pengkun Yang, Chunyan Wang, Lichao Yan
2022 North atlantic university union: International Journal of Circuits, Systems and Signal Processing  
According to the compression and decompression of LZW, the optimal compression effect of LZW algorithm hardware is obtained.  ...  In order to overcome the problems of large error and low precision in traditional power fault record data compression, a new layered lossless compression method for massive fault record data is proposed  ...  In the hardware implementation of LZW algorithm, the dictionary is implemented by the RAM resource in FPGA, while the RAM resource in FPGA is limited, and the dictionary cannot grow unlimited.  ... 
doi:10.46300/9106.2022.16.3 fatcat:pq7ikgqcs5hgbgrhlrv727op3m

Enhanced Image Compression and Processing Scheme

I. Manga, E. J. Garba, A. S. Ahmadu
2021 Current Journal of Applied Science and Technology  
In this paper, an efficient and effective lossless image compression technique based on LZW- BCH lossless image compression to reduce redundancies in the image was presented and image enhancement using  ...  The major aim of lossless image compression is to reduce the redundancy and irreverence of image data for better storage and transmission of data in the better form.  ...  ACKNOWLEDGEMENTS I wish to acknowledge the Tertiary Education Trust Fund (TETFUND) for providing fund to carry out this research.  ... 
doi:10.9734/cjast/2021/v40i3831586 fatcat:f2ze5uqpf5eqhdxxu47k7df2yu

In-memory database acceleration on FPGAs: a survey

Jian Fang, Yvo T. B. Mulder, Jan Hidders, Jinho Lee, H. Peter Hofstee
2019 The VLDB journal  
Therefore, this paper surveys using FPGAs to accelerate in-memory database systems targeting designs that can operate at the speed of main memory.  ...  While FPGAs have seen prior use in database systems, in recent years interest in using FPGA to accelerate databases has declined in both industry and academia for the following three reasons.  ...  The study in [148] presents an efficient LZW by storing the variable-length strings in a pointer table and a character table separately.  ... 
doi:10.1007/s00778-019-00581-w fatcat:32edtb7frfh3xhpziks75lys3y

High-Performance Data Compression-Based Design for Dynamic IoT Security Systems

Maha Aboelmaged, Ali Shisha, Mohamed A. Abd El Ghany
2021 Electronics  
The proposed design seeks to reduce the FPGA reconfiguration time by the application of LZ4 (Lempel-Ziv4) compression and decompression techniques on the ciphers' bitstream files.  ...  IoT technology is evolving at a quick pace and is becoming an important part of everyday life.  ...  For the implementation of the previously mentioned compression/decompression of the bitstreams on the FPGA, an algorithm with a high compression ratio and high decompression rate is required.  ... 
doi:10.3390/electronics10161989 fatcat:j3f7karmmzhrhcaopc5vglgdfe

Lossless Compression Decoders for Bitstreams and Software Binaries Based on High-Level Synthesis

Jian Yan, Junqi Yuan, Philip H. W. Leong, Wayne Luk, Lingli Wang
2017 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
As the density of FPGAs has greatly improved over the past few years, the size of configuration bitstreams grows accordingly.  ...  Moreover, in order to balance the objectives of compression ratio, decompression throughput, and hardware resource overhead, various improvements and optimizations are proposed.  ...  It implements an algorithm that is a variation of the LZ77 algorithm, with the primary focus of providing a very simple and fast decompression method.  ... 
doi:10.1109/tvlsi.2017.2713527 fatcat:usmgiggxybfdnabfhigizkv5g4

An Efficient High-Throughput LZ77-Based Decompressor in Reconfigurable Logic

Jian Fang, Jianyu Chen, Jinho Lee, Zaid Al-Ars, H. Peter Hofstee
2020 Journal of Signal Processing Systems  
The proposed method is about an order of magnitude faster and an order of magnitude more power efficient than a state-of-the-art single-core software implementation.  ...  To best leverage high-bandwidth storage and network technologies requires an improvement in the speed at which we can decompress data.  ...  Leveraging these advantages, the pipelined FPGA designs of LZSS [17, 20] , LZW [30] and Zlib [18, 29] all achieve good decompression throughput.  ... 
doi:10.1007/s11265-020-01547-w fatcat:5pfvjr3czvbpbkvzemxr2ywkqi

A High Throughput No-Stall Golomb-Rice Hardware Decoder

Roger Moussalli, Walid Najjar, Xi Luo, Amna Khan
2013 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines  
In this paper, we present (1) the first no-stall hardware architecture, capable of decompressing streams of integers compressed using the GR method, at a rate of several bytes (multiple integers) per hardware  ...  While occupying 10% of a Xilinx V6LX240T FPGA, the no-stall architecture core achieves a sustained throughput of over 7 Gbps.  ...  The work in [18] describes the FPGA implementation of a multi-bit per cycle GR compressor of ECG signals. Note that compression is orthogonal to decompression (the problem studied in this paper).  ... 
doi:10.1109/fccm.2013.9 dblp:conf/fccm/MoussalliNLK13 fatcat:wzyekmaz5zcxnjkkbg74avsxbm

FPGA Acceleration of Zstd Compression Algorithm

Jianyu Chen, Maurice Daverveldt, Zaid Al-Ars
2021 2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)  
In addition, we optimize the proposed architecture for the specific use case of streaming high-frequency trading data. The optimized kernel is implemented on a Xilinx Alveo U200 board.  ...  With the continued increase in the amount of big data generated and stored in various application domains, such as highfrequency trading, compression techniques are becoming ever more important to reduce  ...  This method is not implemented in hardware since we do not find an efficient way to implement it with low overhead.  ... 
doi:10.1109/ipdpsw52791.2021.00035 fatcat:df57fwvemvhv7driyncjn7fh3y
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