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Speeding-up the fault-tolerance analysis of interconnection networks
2015
2015 International Conference on High Performance Computing & Simulation (HPCS)
Fault-Tolerance in Fat-Trees In interconnection networks, fault-tolerance is usually implemented by using a routing mechanism that provides several alternative paths to communicate every source-destination ...
In particular, we apply this methodology to the fat-tree topology as an example, but it can be applied to any topology. ...
Furthermore, although this work has focused in the fattree topology, the fault-tolerance analysis, and consequently its optimization, can be used on other direct or indirect interconnection networks. ...
doi:10.1109/hpcsim.2015.7237035
dblp:conf/ieeehpcs/GarzonRLG15
fatcat:57ymamp3gngolm3nw3i2g6uiii
Interconnection Structures, Management and Routing Challenges in Cloud-Service Data Center Networks: A Survey
2018
International Journal of Interactive Mobile Technologies
Bandwidth resource fragmentation limits the network agility, and leads to low utilization rates, not only for the bandwidth resources, but also for the servers that run the applications. ...
With Traffic Engineering methods, managers of such networks can adapt for rapid changes in the network traffic among their servers, this can help to provide better resource utilization and lower costs. ...
For DCNs, an efficient routing and forwarding protocol should support for scalable and fault-tolerant environment. ...
doi:10.3991/ijim.v12i1.7573
fatcat:aq2hlunukvbg7oje5nwberja6m
nD-RAPID: a multidimensional scalable fault-tolerant optoelectronic interconnection for high-performance computing systems
2007
Journal of Optical Networking
The design of the router and on-board switching methodology plays a very important role in ensuring an efficient fault-tolerant routing algorithm. ...
The increasing demand for bandwidth coupled with saturating electrical systems is leading the drive for optics as an interconnect technology. ...
The electrical networks chosen for comparison were 2D torus, 3D torus, hypercube, and fat tree. ...
doi:10.1364/jon.6.000465
fatcat:ohce6hkqajct3cxpxdap5xwski
A Family of Fault-Tolerant Efficient Indirect Topologies
2016
IEEE Transactions on Parallel and Distributed Systems
On the one hand, performance and fault-tolerance of interconnection networks are key design issues for high performance computing (HPC) systems. On the other hand, cost should be also considered. ...
Among them, the most commonly used topology is the fat-tree. ...
In CGIN [5] , the network uses an excessive interconnection hardware, tolerating only a single fault. ...
doi:10.1109/tpds.2015.2430863
fatcat:aszihvj6wfclnecdwvxml5mrzy
Routing Techniques in Data Center Networks
[chapter]
2015
Handbook on Data Centers
With the proliferation of internet applications, the demand for DCNs are increasing as they provide efficient platform for data storage to such applications. ...
This involves lot of server to server communication and huge amount of traffic is routed among servers in a data center network. ...
for
multipath routing,
fault tolerance scheme
Wiring overhead
because of fat-tree
topology
Table 2 2 Comparison of Energy-aware routing schemes in data center networks Techniques
Objective ...
doi:10.1007/978-1-4939-2092-1_16
fatcat:gn3f636odbfz5o5e3deugrptcq
Topological exploration for the efficient design of three-dimensional Network on Chip architectures
2020
2020 Third International Conference on Advances in Electronics, Computers and Communications (ICAECC)
Architecture of 3D NoC's ,Topologies , Interconnects, Routing of 3D NoC's are indeed novel areas of exploration. ...
Keywords-Multi Processor System on Chips (MPSoC), topology TSV (Through Silicon Via),Butterfly fattened tree, SPIDERGON, Graphine , nano sacle design. ...
route packets efficiently . ...
doi:10.1109/icaecc50550.2020.9339506
fatcat:nv6b5k2c6jfyhdhia3xw6qkl3e
A fault-tolerant routing strategy for k -ary n -direct s -indirect topologies based on intermediate nodes
2017
Concurrency and Computation
For this reason, an efficient fault-tolerant mechanism is needed to keep the system interconnected, even in the presence of faults. ...
This paper presents a fault-tolerant routing methodology for the KNS topology that degrades performance gracefully in presence of faults and tolerates a large number of faults without disabling any healthy ...
However, we can extend the methodology to KNS topologies that use other indirect subnetworks like fat-trees or RUFT. ...
doi:10.1002/cpe.4065
fatcat:qnui5f3t7jhyta4q7qm7rxhk5a
A Survey and Evaluation of Data Center Network Topologies
[article]
2016
arXiv
pre-print
The large scale nature of data centers requires careful planning of compute, storage, network nodes, interconnection as well as inter-communication for their effective and efficient operations. ...
Each data center consists of massive compute, network and storage resources connected with physical wires. ...
Acknowledgments Many thanks to Prof Tushar Krishna for guiding us on every step of the project, for providing us with computing resources for our simulations and experiments, for giving us periodic feedback ...
arXiv:1605.01701v1
fatcat:bcy427mizbct3g5mfeyia5orzm
Overlapped Subarray Segmentation: An Efficient Test Method for Cellular Arrays
1993
VLSI design (Print)
This approach detects bridging faults in addition to stuck-at faults. Such bridging faults are a significant problem in arithmetic circuits. ...
This paper presents a new test approach that is suitable for repetitive structures such as cellular arrays. ...
We developed efficient methods for testing packet-switched multistage interconnection networks. ...
doi:10.1155/1993/76586
fatcat:zswn5ilxsjeibldh5u6b2t2jx4
An efficient hardware-software approach to network fault tolerance with InfiniBand
2009
2009 IEEE International Conference on Cluster Computing and Workshops
Using the proposed approach, the applications run to completion without restart on emulated network faults and acceptable overhead for benchmarks executing for a longer period of time. ...
In this paper, we specifically focus on the network component failure and propose a hybrid hardware-software approach to handling network faults. ...
We also discuss the methodology of emulating network faults, and the behavior of Hybrid-IBNFT in the presence of emulated network faults. ...
doi:10.1109/clustr.2009.5289168
dblp:conf/cluster/VishnuKP09
fatcat:yuohjqnrwrh53j4kdbmyyelp5a
Techniques for Optimizing Power Utilization in Data Center Network Architectures: A Survey Report
2016
Indian Journal of Science and Technology
Objectives: The Data Center Network (DCN) is the collection of diverse classes of resources providing storage, processing and network functionalities. ...
Findings: In this study, we presented a survey on various techniques and methodologies that are used to reduce the amount of power consumed in the data centers. ...
DCell implements a fault-tolerant routing algorithm to prevent the network from various kinds of failures. The energy consumption increases when the count of miniswitches increases. ...
doi:10.17485/ijst/2016/v9i37/102066
fatcat:kcpbc43jdvhj3adpvue2vps46e
Applying MPLS Technique as On-Chip Communication Means for Network-on-Chip with Mesh Topology
2021
Zenodo
This paper describes designing an efficient mesh topology Network-on-Chip system by employing MPLS protocol as an on-chip communication technique. ...
Experimental results are compared with two simulators: wormhole equipped with virtual channels; and MPLS-based fat tree network-on-chip systems. ...
Consequently, in mesh topology the deterministic routing produces low routing latency and good reliability when the network is not under congestion status. Fault tolerance: mesh as an interconnection ...
doi:10.5281/zenodo.4514974
fatcat:mgpzc6m5dvhyngdy66lkchlttm
Design, Synthesis, and Test of Networks on Chips
2005
IEEE Design & Test of Computers
Kumar proposed a mesh-based interconnect architecture called Cliché (Figure 1a ). 5 Grecu et al. 6 describe an interconnect architecture based on the butterfly fat-tree (BFT) topology for a networked ...
Figure 1 . 1 Network-on-a-chip (NoC) interconnect architectures: Cliché (a), butterfly fat-tree (BFT) topology (b), Octagon MP-SoC (c), irregular application-specific template (d). ...
doi:10.1109/mdt.2005.108
fatcat:ftg32fzp2jelppgskbqb34ehiy
A theory and methodology for combining data centre networks
2012
2012 19th International Conference on High Performance Computing
Existing methods for routing of interconnection networks are optimized for a small group of well defined topologies. ...
Thereafter we present a theory and a methodology for combining multiple networks in a deadlock-free manner. ...
These seminal papers have later formed the basis for almost all developments within routing of interconnection networks, spanning problems areas such as fault tolerance [5] , [6] , [7] , dynamic reconfiguration ...
doi:10.1109/hipc.2012.6507493
dblp:conf/hipc/Sem-JacobsenLL12
fatcat:omcrijxrlncaxhvt7tpwob5npe
Multidimensional and Reconfigurable Optical Interconnects for High-Performance Computing (HPC) Systems
2009
Journal of Lightwave Technology
as an interconnect technology of choice for high-performance computing (HPC) systems. ...
Fault-tolerance in -RAPID is enabled through a multidimensional architecture. ...
Prior work in fault-tolerant optical interconnects include a hypercube connected rings with a depth-first search-based fault-tolerant routing algorithm (HCRNet, [8] ); a three-stage Clos network to overcome ...
doi:10.1109/jlt.2009.2026187
fatcat:5mjta62o5jfpfdvyqoayzpvxhq
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