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FPGA Implementation of Real-Time Compressive Sensing with Partial Fourier Dictionary

Yinghui Quan, Yachao Li, Xiaoxiao Gao, Mengdao Xing
2016 International Journal of Antennas and Propagation  
To solve these problems efficiently, the correlation optimization is implemented by fast Fourier transform (FFT) and the large scale least square problem is implemented by Conjugate Gradient (CG) technique  ...  However, reconstruction algorithms are computing demanding and software implementation of these algorithms is extremely slow and power consuming.  ...  Conflict of Interests The authors declare that there is no conflict of interests regarding the publication of this paper.  ... 
doi:10.1155/2016/1671687 fatcat:26y7hlsvtjaepcwlsgzrumajfi

Efficient hardware implementation of hybrid cosine-fourier-wavelet transforms on a single FPGA

K. Wahid, S. Shimu, M. Islam, D. Teng, Moon Ho Lee, S-B. Ko
2009 2009 IEEE International Symposium on Circuits and Systems  
This paper presents an efficient hardware implementation of a hybrid architecture to compute three 8point transforms -the Discrete Cosine Transform, the Discrete Fourier Transform, and the Discrete Wavelet  ...  of 944 Megabits/sec when synthesized onto an Altera FPGA device.  ...  ACKNOWLEDGMENT The authors would like to acknowledge the Natural Science and Engineering Research Council of Canada (NSERC) for its support to this research work.  ... 
doi:10.1109/iscas.2009.5118265 dblp:conf/iscas/WahidSITLK09 fatcat:j6p4ix74urhsrgb2o3io2dni4y

Design and Implementation of an Accelerated Gabor Filter Bank Using Parallel Hardware [chapter]

Nikolaus Voß, Bärbel Mertsching
2001 Lecture Notes in Computer Science  
The actual implementation is preceded by an analysis of the algorithm analyzing the effects of reduced-accuracy calculus and the possibility of parallelizing the process.  ...  This paper describes how this can be overcome by a hardware-implementation of the filter algorithm.  ...  This way, in addition to the number representations, various algorithms for two-dimensional Fourier transform were evaluated for an efficient hardware implementation.  ... 
doi:10.1007/3-540-44687-7_46 fatcat:i2rxw5i2azfkbishlwkpts46yq

An FPGA-Based Quantum Computing Emulation Framework Based on Serial-Parallel Architecture

Y. H. Lee, M. Khalil-Hani, M. N. Marsono
2016 International Journal of Reconfigurable Computing  
Quantum Fourier transform and Grover's search are chosen as case studies in this work since they are the core of many useful quantum algorithms.  ...  In this paper, an efficient hardware emulation method that employs a serial-parallel hardware architecture targeted for field programmable gate array (FPGA) is proposed.  ...  Proposed FPGA-Based Hardware Emulation This section presents our approach in modelling quantum Fourier transform and Grover's search algorithms for FPGA emulation.  ... 
doi:10.1155/2016/5718124 fatcat:zgnbadr32vezxargw7lg735o5q

Rapid Prototyping And Fpga-In-The-Loop Verification Of A Dfrft-Based Ofdm System

Atul Kumar, Maurizio Magarini, Stefano Olivieri
2018 Zenodo  
Publication in the conference proceedings of EUSIPCO, Kos island, Greece, 2017  ...  which is the same as that of fast Fourier transform (FFT), the efficient implementation of DFT.  ...  Nowadays, discrete fractional Fourier transform (DFrFT) is emerging as an efficient tool for performing timefrequency analysis in many fields of digital signal processing [1] .  ... 
doi:10.5281/zenodo.1160009 fatcat:hectp34w7jdlpc5m22g5dlhety

Efficient image reconstruction using partial 2D Fourier transform

L. Deng, C.-L. Yu, C. Chakrabarti, J. Kim, V. Narayanan
2008 2008 IEEE Workshop on Signal Processing Systems  
In this paper we present an efficient way of doing image reconstruction using the 2D Discrete Fourier transform (DFT).  ...  We also describe the implementation of the new reconstruction algorithm on a Xilinx Virtex-II Pro-100 FPGA.  ...  Xiaobai Sun in Duke University for assistance in the decomposition algorithm for 2D DFT.  ... 
doi:10.1109/sips.2008.4671736 dblp:conf/sips/DengYCKN08 fatcat:zd4ugqwmizbyxircjmznlrahky

Efficient FPGA-based FIR – architecture and its significance in ultrasonic signal processing

Kumar Anubhav Tiwari, Armantas Ostreika, Jurate Platuziene
2017 Journal of Vibroengineering  
The presented work demonstrates the most suitable architecture for the FPGA-based signal processing which makes available various real-time filtering algorithms, such as band pass, high pass, low pass,  ...  The processor was implemented with the fixed-point arithmetic using VHDL, which can be downloadable on FPGA device.  ...  Acknowledgement This research work was supported by the Multimedia Engineering Department and Ultrasound Research Institute, Kaunas University of Technology, Lithuania.  ... 
doi:10.21595/jve.2017.18932 fatcat:jk5ubceoevgyfade65afeukvbq

2D Discrete Fourier Transform with simultaneous edge artifact removal for real-time applications

Faisal Mahmood, Mart Toots, Lars-Goran Ofverstedt, Ulf Skoglund
2015 2015 International Conference on Field Programmable Technology (FPT)  
Two-Dimensional (2D) Discrete Fourier Transform (DFT) is a basic and computationally intensive algorithm, with a vast variety of applications. 2D images are, in general, non-periodic, but are assumed to  ...  We use a periodic-plus-smooth decomposition based artifact removal algorithm optimized for FPGA implementation, while still achieving real-time (>23 frames per second) performance for a 512×512 size image  ...  Most FPGA based 2D FFT implementations rely upon repeated invocations of 1D FFTs by row and column decomposition (RCD) with efficient use of external memory [2] [3] [4] .  ... 
doi:10.1109/fpt.2015.7393157 dblp:conf/fpt/MahmoodTOS15 fatcat:idkhohxhsndtpebw5xgeomtpvm

Pipelined Architecture of Multi-Band Spectral Subtraction Algorithm for Speech Enhancement

Mohammed Bahoura
2017 Electronics  
In this paper, a new pipelined architecture of the multi-band spectral subtraction algorithm has been proposed for real-time speech enhancement.  ...  The multi-band algorithm has been developed to reduce the additive colored noise that does not uniformly affect the entire frequency band of useful signal.  ...  Acknowledgments: This research is financially supported by the Natural Sciences and Engineering Research Council (NSERC) of Canada. Conflicts of Interest: The author declare no conflict of interest.  ... 
doi:10.3390/electronics6040073 fatcat:lun2ori75vbkbnzfqxonn4tvvu

Design and Implementation of Floating Point FFT Processor using VHDL

2013 IOSR Journal of VLSI and Signal processing  
The Fast Fourier Transform (FFT) is a capable algorithm to compute the Discrete Fourier Transform (DFT) and it's inverse. It has a number of applications in the field of signal processing.  ...  This paper describes two fused floating-point operations and applies them to the implementation of Fast Fourier Transform (FFT) processors using VHDL.  ...  Fourier Transform of a data vector.  ... 
doi:10.9790/4200-0331318 fatcat:7sb3xfivofc3pk255xihpgopuy

High-throughput implementation of a million-point sparse Fourier Transform

Abhinav Agarwal, Haitham Hassanieh, Omid Abari, Ezz Hamed, Dina Katabi, Arvind
2014 2014 24th International Conference on Field Programmable Logic and Applications (FPL)  
In this paper, we present a high-throughput FPGA implementation that performs a million-point sparse Fourier Transform on frequency-sparse input data, generating the largest 500 frequency component locations  ...  The emergence of data-intensive problems in areas like computational biology, astronomy, medical imaging, etc. has emphasized the need for fast and efficient very large Fourier Transforms.  ...  Today, efficient millionpoint Fast Fourier Transforms (FFTs) are not practical.  ... 
doi:10.1109/fpl.2014.6927450 dblp:conf/fpl/AgarwalHAHKA14 fatcat:algozemhmrhh3n5prirgjirpfy


Azlan Muharam, Afandi Ahmad
2017 Jurnal Teknologi  
In conclusion, the overall picture of the image processing landscape, where several researchers more focused on software implementations and various combinations of software and hardware implementation  ...  This paper thoroughly reviews the recent advances in medical image compression mainly in terms of types of compression, software and hardware implementations and performance evaluation.  ...  Figure 4 Block diagram of proposed method of six stages of compression algorithm [58] An analysis of the discrete fractional Fourier transform (DFT) based medical image compression using a hybrid encoding  ... 
doi:10.11113/jt.v79.7873 fatcat:ygxpova2xbb3zd3yweyfwgph74

Fixed-point realization of fast nonlinear Fourier transform algorithm for FPGA implementation of optical data processing

Anastasiia Vasylchenkova, Dmytro Salnikov, Dmytro Karaman, Oleg Vasylchenkov, Yaroslav E. Prylepskiy, Anatoly V. Zayats, Mario Bertolotti, Alexei M. Zheltikov
2021 Nonlinear Optics and Applications XII  
The main component of the algorithm is the matrix-multiplier unit, implemented on field-programmable gate arrays (FPGA) and used in our study for the estimation of required hardware resources.  ...  However, the mathematical complexity of NFT algorithms and the noticeable distinction of the latter from the "conventional" (Fourier-based) methods make it difficult to adapt this approach for practical  ...  The numerically evaluated auxiliary scattering functions are therefore given as: a(ξ) b(ξ) = e iξT e −iξT · N m=1 M m · e iξT 0 . (4) The widely used fast NFT algorithm is based on the fast Fourier transform  ... 
doi:10.1117/12.2588735 fatcat:bub7fcfznbcebjl3xfsvc5e234

FPGA implementation made easy for applied digital signal processing courses

N. Kehtarnavaz, S. Mahotra
2011 2011 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)  
Our approach is based on the LabVIEW FPGA Module which allows FPGA implementation to be achieved in a time-efficient manner via more intuitive graphical coding.  ...  Index Terms -Applied digital signal processing courses, FPGA implementation of signal processing algorithms, LabVIEW FPGA, hybrid FPGA programming  ...  fast Fourier transform (FFT), discrete cosine transform (DCT), and discrete wavelet transform (DWT) using the LabVIEW FPGA Module.  ... 
doi:10.1109/icassp.2011.5947089 dblp:conf/icassp/KehtarnavazM11 fatcat:ukfwojgdkfh6xp5ooxpqquavj4

An Fpga Based Parametrisable System For Discrete Orthogonal Transforms Implementation

Abbes Amira, Ahmed Bouridane, Ali Roula Mohammed, Fatih Kurugollu
2002 Zenodo  
Publication in the conference proceedings of EUSIPCO, Toulouse, France, 2002  ...  It is the aim of this paper to develop efficient architectures, ideally suited for a fast computation of the DOTs using an FPGA based parameterisable system.  ...  The MBWM algorithm has been used for the implementation of the systolic architecture, due to it suitability for a Virtex FPGA implementation [7] .  ... 
doi:10.5281/zenodo.53686 fatcat:3gsgpflqjffsrhpr7rh7kpkina
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