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FPGA test time reduction through a novel interconnect testing scheme
2002
Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays - FPGA '02
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This new testing architecture reduces switching matrix test time by 66% and the diagnosis time by 72%. The additions are transparent to the users both in terms of speed and functionality. ...
We present an approach to speed up testing FPGA interconnect by reconfiguring it during the test. ...
ACKNOWLEDGEMENTS We would like to thank the Canadian Microelectronics Corporation (CMC) for providing services and funding to produce a custom designed FPGA device. ...
doi:10.1145/503048.503069
dblp:conf/fpga/McCrackenZ02
fatcat:pjsjaxwzbvhxvcqmmk7cwkxdsy
FPGA test time reduction through a novel interconnect testing scheme
2002
Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays - FPGA '02
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This new testing architecture reduces switching matrix test time by 66% and the diagnosis time by 72%. The additions are transparent to the users both in terms of speed and functionality. ...
We present an approach to speed up testing FPGA interconnect by reconfiguring it during the test. ...
ACKNOWLEDGEMENTS We would like to thank the Canadian Microelectronics Corporation (CMC) for providing services and funding to produce a custom designed FPGA device. ...
doi:10.1145/503066.503069
fatcat:f5bnfabwp5grja66zcf433ezby
Fault-Resilient Lightweight Cryptographic Block Ciphers for Secure Embedded Systems
2014
IEEE Embedded Systems Letters
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To the best of the author's knowledge, there has been no error detection scheme presented in the literature for the XTEA to date. ...
Finally, field-programmable gate array (FPGA) implementations of these proposed error detection structures are presented to assess their efficiency and overhead. ...
Another most common and frequently occurring type of fault is in SRAM cells, where particular cells maybe flipped. ...
doi:10.1109/les.2014.2365099
fatcat:bmpoyosicbh67bffjc5d2isrou
Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories
2005
Journal of electronic testing
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This paper presents an analysis of dynamic faults in core-cell of SRAM memories. ...
In this paper, we demonstrate that read or write operations on a cell involve a stress on the other cells of the same word line. ...
For example we still use the same Infineon SRAM architecture. ...
doi:10.1007/s10836-005-1169-1
fatcat:clwvjqaazrf47ht5vmvnheqjg4
Field Programmable Gate Array Applications—A Scientometric Review
2019
Computation
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These publications show the vast range of applications based on FPGAs, from the new mechanism that enables the magnetic suspension system for the kilogram redefinition, to the Mars rovers' navigation systems ...
Also, we present an evolution and trend analysis of the related applications. ...
An efficient BIST architecture for delay faults
in the logic cells of symmetrical SRAM-based FPGAs. J. Electron.-Test.-Theory Appl. 2006, 22, 161-172.
[CrossRef]
387. Pundir, A.; Sharma, O. ...
doi:10.3390/computation7040063
fatcat:wxtatzsvvnfopghdfl25hcfc2a
SABRE: a bio-inspired fault-tolerant electronic architecture
2013
Bioinspiration & Biomimetics
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Acknowledgments This research work is supported by the Engineering and Physical Sciences Research Council of the United Kingdom under Grant Number EP/F062192/1 and EP/F067623/1. ...
The FPGA based simulation of the SMove processor consists of FUs for both the thresholding and scaling of the sensor signals, one of which is made up of 15 UX cells and the others use the standard FPGA ...
Allowing for checking of SET and permanent SEE occurring in the functional logic of the cell. ...
doi:10.1088/1748-3182/8/1/016003
pmid:23302298
fatcat:u6pv3nqw35e6rd7yjpjwx74die
2021 Index IEEE Transactions on Circuits and Systems I: Regular Papers Vol. 68
2021
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
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The Author Index contains the primary entry for each item, listed under the first author's name. ...
Note that the item title is found only under the primary entry in the Author Index. ...
., +, TCSI Jan. 2021 322-335 Towards Low Latency and Resource-Efficient FPGA Implementations of the MUSIC Algorithm for Direction of Arrival Estimation. ...
doi:10.1109/tcsi.2021.3134605
fatcat:txqhqj7nvnh6pp5dqloynq5jku
Foundations of Secure Scaling (Dagstuhl Seminar 16342)
2017
Dagstuhl Reports
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While scaling is generally thought of as beneficial to the resulting implementations, this does not hold for secure electronic design. ...
This report documents the program and the outcomes of Dagstuhl Seminar 16342 "Foundations of Secure Scaling". ...
For instance, in the Bernstein's cache timing attack, we try to invoke the AES encryption by .xing part of the input, and randomize other parts of the inputs and obtain the total time for the encryption ...
doi:10.4230/dagrep.6.8.65
dblp:journals/dagstuhl-reports/BatinaBSS16
fatcat:qya6rznvonbi7pfic7ocbxwkea
A Built-In Self-Testing Method for Embedded Multiport Memory Arrays
2005
IEEE Transactions on Instrumentation and Measurement
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Wen-Ben Jone, for the guidance and constructive criticism that he provided throughout my work. He was always ready to provide his guidance and help in solving problems, even during weekends. ...
Jone, for all that you have done for us. ...
In this thesis, we develop an efficient BIST architecture that can test multiple dual-port memory modules with different sizes concurrently. ...
doi:10.1109/tim.2005.855093
fatcat:knkdhn6dl5eevlb34chu6ao6fy
DeSyRe: On-demand system reliability
2013
Microprocessors and microsystems
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In the face of such changes in the technological landscape, current solutions for fault tolerance are expected to introduce excessive overheads in future systems. ...
In our attempt to reduce the overheads of fault-tolerance, only a small fraction of the chip is built to be fault-free. ...
In the first case, the substitutable unit can be an entire sub-component (e.g. a microprocessor's pipeline stage), while in the latter case an FPGA logic cell. ...
doi:10.1016/j.micpro.2013.08.008
fatcat:jg623r4hmngthk652u7qi6ibme
Practice Problems for Hardware Engineers
[article]
2021
arXiv
pre-print
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2021 pre-print arXiv:2110.06526v2 fatcat:qg3wlnsaszannnuylumg3n342uOther Versions
The first edition consists of more than 150 problems and their solutions which the author has used in his VLSI, logic, and architectures courses while teaching at USC. ...
It may also be used as a practice resource while taking courses in VLSI, logic and computer architecture design. ...
Assume transition time is defined based on 20%VDD and 80%VDD crossing points. e) Design a dual rail Domino logic for W.
Consider the CMOS SRAM cell shown in the following figure. ...
arXiv:2110.06526v3
fatcat:hquxq53eqrcetlsgwa7i34wsri
Design of a soft-error robust microprocessor
2009
Microelectronics Journal
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In the work (SHIVAKUMAR et al, 2002) were analyzed the trends in the SER for SRAM cells, latches and combinational circuits. ...
The effects of these physical faults on the IC can be represented by logical faults based on the fault model discussed in chapter 2. ...
Fault Injection by Simulation Fault injection experiments were performed through the post-layout gate-level simulation discussed in section 5.1.1. The goal of this simulation experiment is to verify ...
doi:10.1016/j.mejo.2008.10.001
fatcat:pfqera6sdnbshgwa3n7ptqh76u
BIST of delay faults in the logic architecture of symmetrical FPGAs
Proceedings. 10th IEEE International On-Line Testing Symposium
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In this paper, we propose a BIST scheme for exhaustive testing all delay faults in the logic architecture of symmetrical FPGAs. ...
Our technique enables the detection of delay faults in the logic architecture and consists in chaining the logic cells in a specific way. ...
the end of the test process. On the benefits side, our BIST provides a test with large delay fault coverage within the logic architecture and reduced test sequence. ...
doi:10.1109/olt.2004.1319686
fatcat:lljgf6fm6razbp6wbfoci5yau4
Ultra-Low-Power Design and Hardware Security Using Emerging Technologies for Internet of Things
2017
Electronics
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However, when CMOS logic is operating at the sub-threshold voltage level, a significant increase in leakage power and circuit delay occurs [6] . ...
Clearly, energy efficient mobile computing requires an ultra-low-power system design [18] . Achieving a very low average power for a wireless system typically makes extensive use of duty cycling. ...
This work is supported in part by the Florida Center for Cybersecurity (FC 2 ). Author Contributions: Jiann-Shiun Yuan organizes the materials and writes the manuscript. ...
doi:10.3390/electronics6030067
fatcat:ozssarlb2ng5pcdsupo2hljyna
A high-throughput low-cost AES cipher chip
Proceedings. IEEE Asia-Pacific Conference on ASIC,
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We propose an efficient hardware implementation of the AES (Advanced Encryption Standard) algorithm, with key expansion capability. ...
Testability of the design also is considered. The hardware cost of the AES design is about 58.5K gates. ...
Acknowledgment The authors would like to thank Prof. Chi-Chao Chao of NTHU for his valuable comments on the basis transformation. ...
doi:10.1109/apasic.2002.1031538
fatcat:5cjxymriuralrhmhvv77hganei
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