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An Automatic Compiler Optimizations Selection Framework for Embedded Applications

Shih-Hao Hung, Chia-Heng Tu, Huang-Sen Lin, Chi-Meng Chen
2009 2009 International Conference on Embedded Software and Systems  
for an embedded application.  ...  This paper aims at system-wide compiler optimizations selection for embedded applications.  ...  AN AUTOMATIC PERFORMANCE TUNING FRAMEWORK In this section, we describe the general design of the framework that we used to apply automatic compiler options selection algorithms for embedded applications  ... 
doi:10.1109/icess.2009.86 dblp:conf/icess/HungTLC09 fatcat:qh4mbsdxcffl3fduxugp5fe5ti

Customizing Software Toolkits for Embedded Systems-on-Chip [chapter]

Ashok Halambi, Nikil Dutt, Alex Nicolau
2001 IFIP Advances in Information and Communication Technology  
As the software content in these emerging embedded SOCs begins to dominate the SOC design process, there is a critical need for support of an integrated software development environment (including compilers  ...  Modern Embedded Systems-on-Chips (SOCs) will allow the system designer to customize Intellectual Property (IP) cores (fixed and programmable), together with custom logic and large amounts of embedded memories  ...  The Transmutations framework is a part of the EXPRESS retargetable compiler for embedded systems.  ... 
doi:10.1007/978-0-387-35409-5_9 fatcat:4ynfl3yzgrghbj2yiub6yamksu

Early Stage Automatic Strategy for Power-Aware Signal Processing Systems Design

Carlo Sau, Nicola Carta, Luigi Raffo, Francesca Palumbo
2015 Journal of Signal Processing Systems  
While embedded multi-core systems will look to play an important role ahead for application designs, many challenging problems remain to be resolved.  ...  Applications, programming models, compilers, API designs, architecture designs, and software tools all need to contribute to the advance of embedded multi-core computing for signal processing, pixel processing  ...  A couple of optimization constructs have also been offered for rapid program optimization.  ... 
doi:10.1007/s11265-015-0999-z fatcat:acmbvgxxirfp3mb3zi7io3nqly

A framework for Compiler Level statistical analysis over customized VLIW architecture

Amir Hossein Ashouri, Vittorio Zaccaria, Sotirios Xydis, Gianluca Palermo, Cristina Silvano
2013 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)  
The proposed methodology provides the designer with an integrated framework to automatically (i) generate optimized applicationspecific VLIW architectural configurations and (ii) analyze compiler level  ...  Very Long Instruction Word (VLIW) application specific processors represent an attractive solution for embedded computing, offering significant computational power with reduced hardware complexity.  ...  The proposed methodology provides the designer with an integrated framework to automatically (i) generate optimized application specific VLIW architectural configurations and (ii) analyse in a fine-grained  ... 
doi:10.1109/vlsi-soc.2013.6673262 dblp:conf/vlsi/AshouriZXPS13 fatcat:ts5qanwymndwhetynb2bwodsga

Embedded computer architecture and automation

B. Ramakrishna Rau, M.S. Schlansker
2001 Computer  
The distinct requirements of embedded computing, coupled with emerging technologies, will stimulate system and processor specialization, customization, and computer architecture automation.  ...  Acknowledgments Our present and past colleagues in the Compiler and Architecture Research group at Hewlett-Packard Laboratories who worked with us in developing the PICO system have greatly influenced  ...  For an application written in C, it automatically architects a set of Paretooptimal system designs and emits the structural VHDL for the hardware components as well as the compiled software code.  ... 
doi:10.1109/2.917544 fatcat:e5pszcfco5fjziqjifbuu7vnwa

A Bayesian network approach for compiler auto-tuning for embedded processors

Amir Hossein Ashouri, Giovanni Mariani, Gianluca Palermo, Cristina Silvano
2014 2014 IEEE 12th Symposium on Embedded Systems for Real-time Multimedia (ESTIMedia)  
This paper proposes a machinelearning approach for reducing the cost of the compiler autotuning phase and to speedup the application performance in embedded architectures.  ...  The selected set of solutions (less than 10% of the search space) demonstrated to be very close to the optimal sequence of transformations, showing also an applications performance speedup up to 2.8 (1.5  ...  , while the target architecture where the application executes (i.e. the architecture for which the application shall be optimized) is an embedded ARMbased platform.  ... 
doi:10.1109/estimedia.2014.6962349 dblp:conf/estimedia/AshouriMPS14 fatcat:ocjync5hpza37jtui67nw3oe3e

Automatic Compilation of C Applications for FPGA-Based Hardware Acceleration

Lieu My Chuong, Yan Lin Aung, Siew-Kei Lam, Thambipillai Srikanthan, Lim Chai Soon
2011 2011 Fourth International Symposium on Parallel Architectures, Algorithms and Programming  
We present a design exploration framework that automatically compiles C applications to realize efficient custom coprocessor structures for hardware acceleration on the reconfigurable logic.  ...  We show that the proposed design exploration framework can automatically generate Register Transfer Level (RTL) codes from Cfunctions that outperform the commercial Altera C2H RTL generator by about 40%  ...  , which is widely used in embedded applications.  ... 
doi:10.1109/paap.2011.70 dblp:conf/paap/ChuongALSL11 fatcat:rcn4sjaupncmxc46us5celqwmm

Finding effective optimization phase sequences

Prasad Kulkarni, Wankang Zhao, Hwashin Moon, Kyunghwan Cho, David Whalley, Jack Davidson, Mark Bailey, Yunheung Paek, Kyle Gallivan
2003 Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems - LCTES '03  
In addition, VISTA provides support for automatically using performance information to select the best optimization sequence among several attempted.  ...  In this paper, we describe support in VISTA, an interactive compilation system, for finding effective sequences of optimization phases.  ...  An environment that allows a user to easily tune the sequence of optimization phases for each function in an embedded application can be very beneficial.  ... 
doi:10.1145/780733.780735 fatcat:xhbfchesbrc3rdnqj4qqg7qzea

Finding effective optimization phase sequences

Prasad Kulkarni, Wankang Zhao, Hwashin Moon, Kyunghwan Cho, David Whalley, Jack Davidson, Mark Bailey, Yunheung Paek, Kyle Gallivan
2003 SIGPLAN notices  
In addition, VISTA provides support for automatically using performance information to select the best optimization sequence among several attempted.  ...  In this paper, we describe support in VISTA, an interactive compilation system, for finding effective sequences of optimization phases.  ...  An environment that allows a user to easily tune the sequence of optimization phases for each function in an embedded application can be very beneficial.  ... 
doi:10.1145/780731.780735 fatcat:ys3xk7kadbf57fzcnjb3dgj3ji

SchedCust: Design & Development of scheduling policy customization framework for ARM based System on Chip

Jasleen Kaur, SRN Reddy
2020 Procedia Computer Science  
Selecting a right scheduling strategy for the specific embedded application has a significant impact on system's performance.  ...  Abstract Selecting a right scheduling strategy for the specific embedded application has a significant impact on system's performance.  ...  Acknowledgement This work is supported by Microsoft University Relations, Finland under the research grant of project Mobile Education Kit-2 (Mek2) to Indira Gandhi Delhi Technical University for women  ... 
doi:10.1016/j.procs.2020.04.068 fatcat:usrozn4lxvdkpnqkrlifl6yqly

Evaluation of Tuning and Normalized Tuning Time using an Effective and Automated Framework pertained to Benchmark Applications

J. Andrews, T.Sasikala T.Sasikala
2013 International Journal of Computer Applications  
Tuning compiler optimization for a given application of particular computer architecture is not an easy task, because modern computer architecture reaches higher levels of compiler optimization.  ...  In this paper, machine learning algorithm has been modified and used to reduce the complexity of selecting suitable compiler options for programs running on a specific hardware platform.  ...  Automatic Compiler Optimizations Selection Framework for Embedded Applications.In proceddings .of international .conference on Embedded Software and Systems,pp.381-387. [4] Z.Pan and R.Eigenmann2006.Fast  ... 
doi:10.5120/11874-7679 fatcat:agxtshetdjan5nszeugkietmju

Automatic generation of application-specific accelerators for FPGAs from python loop nests

David Sheffield, Michael Anderson, Kurt Keutzer
2012 22nd International Conference on Field Programmable Logic and Applications (FPL)  
It does this to uncover parallelism and divide computation between multiple parallel processing elements (PEs) that are automatically generated through high-level synthesis of the optimized loop body.  ...  We present Three Fingered Jack, a highly productive approach to mapping vectorizable applications to the FPGA.  ...  This motivates a selective and embedded approach to design: the programmer selects only certain computations for acceleration. These computations are embedded as a subset of a high-level language.  ... 
doi:10.1109/fpl.2012.6339372 dblp:conf/fpl/SheffieldAK12 fatcat:hphpwnv4uvdkxlwhptkr6p7ery

Experiments with the LARA aspect-oriented approach

José G.F. Coutinho, Tiago Carvalho, Sérgio Durand, João M.P. Cardoso, Ricardo Nobre, Pedro C. Diniz, Wayne Luk
2012 Proceedings of the 11th annual international conference on Aspect-oriented Software Development Companion - AOSD Companion '12  
embedded systems.  ...  All these components can be coordinated as part of an elaborate application mapping strategy using LARA.  ...  Acknowledgments Acknowledgments This work was partially supported by the European Co munity's Framework Programme 7 (FP7) under contract Any opinions, findings, and con recommendations expressed in this  ... 
doi:10.1145/2162110.2162129 dblp:conf/aosd/CoutinhoCDCNDL12 fatcat:7kzplftilfdy7jkr5kt4k4taoi

Selection of instruction set extensions for an FPGA embedded processor core

B.F. Veale, J.K. Antonio, M.P. Tull, S.A. Jones
2006 Proceedings 20th IEEE International Parallel & Distributed Processing Symposium  
A design process is presented for the selection of a set of instruction set extensions for the PowerPC 405 processor that is embedded into the Xilinx Virtex Family of FPGAs.  ...  The proposed design process gathers execution statistics for a target application through profiling or simulation.  ...  A Framework for Automatic Instruction Set Selection Motivated by Linear Programming models used to optimize the parameters of ASIPs using architectural exploration in [2] , we propose a formal optimization  ... 
doi:10.1109/ipdps.2006.1639455 dblp:conf/ipps/VealeATJ06 fatcat:vagshmeeinca3l77o4kwl3cdpi

Less is More

Kyriakos Georgiou, Craig Blackmore, Samuel Xavier-de-Souza, Kerstin Eder
2018 Proceedings of the 21st International Workshop on Software and Compilers for Embedded Systems - SCOPES '18  
This observation has been validated on two embedded processors, namely the ARM Cortex-M0 and the ARM Cortex-M3, using two different versions of the LLVM compilation framework; v3.8 and v5.0.  ...  Experimental evaluation with 71 embedded benchmarks demonstrated performance gains for at least half of the benchmarks for both processors.  ...  Zbigniew Chamski for his valuable comments and helpful suggestions.  ... 
doi:10.1145/3207719.3207727 dblp:conf/scopes/GeorgiouBSE18 fatcat:wxkcsttcvvhklcotvt4rl7qlvu
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