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The CMS barrel muon track finder and upgrades for HL-LHCs [article]

Stavros Mallios, University Of Ioannina, University Of Ioannina
2020
In this dissertation, the contributions to the Phase-2 CMS detector upgrade are presented, comprised of the design and testing of a new high-speed link protocol for the Phase-2 trigger, the integration  ...  Finally, the new demonstrator board, features a 20 nm technology Field Programmable Gate Array (FPGA) and it is capable of running sixteen optical links at 16 Gbps, with excellent Bit Error Ratio (BER)  ...  Firstly, a low latency asynchronous protocol for high speed links was designed, implemented and tested.  ... 
doi:10.26268/heal.uoi.9814 fatcat:urlmyrp7jbhcfnqb3jxmdkim3e

Digital Centric Multi-Gigabit SerDes Design and Verification

Markus Roman Müller
2018
Digitally Controlled Oscillator (DCO) To meet low jitter specications required by high speed serial links, an LC tank has to be used in the DCO [36] .  ...  For this multi-protocol SerDes, PRBS generators and checkers for dierent standard polynomials are included, specically: Figure 3 . 3 67: Dierent types of loopback locations: 1) near end serial 2) far  ... 
doi:10.11588/heidok.00023972 fatcat:qirrggdrvrgibkvkvznx5vmzpi

Design of Multi-Gigabit Network Interconnect Elements and Protocols for a Data Acquisition System in Radiation Environments

Sven Andreas Chris Markus Schatral
2018
Special focus is placed on the physical layers and network interface elements from high-speed serial LVDS interconnects up to 20 Gb/s SSTL links in state-of-the-art process technology.  ...  Special configured serial bidirectional point-to-point interconnects are proposed to realize high speed data transmission, slow control access, synchronization and global clock distribution on unified  ...  As already mentioned, a parallel clock P_cdr_clk is derived from the high-speed serial receive clock, which is recovered from the link.  ... 
doi:10.11588/heidok.00024533 fatcat:mbzds6fqnrerlgmtxhq7od5wbe

All-Digital Clock Calibration for Source-Synchronous High-Speed I/O Links Based on Phase-to-Digital Conversion

Nico Angeli
2020
Wire-linked high-speed interfaces play an important role in modern computing systems.  ...  A common challenge in all parallel high-speed I/O links is the calibration of the ideal sampling time for each individual data link.  ...  clock calibration of high-speed I/O links.  ... 
doi:10.25534/tuprints-00012975 fatcat:2mcmwgbkcbespi4ubhxqkzsw2a

A Silicon Photomultiplier Readout ASIC for the Mu3e Experiment

Huangshan Chen
2018
To search for such rare events, extremely high muon decay rate, good background suppression and high detector efficiencies are required.  ...  This demands an excellent momentum, vertex and timing resolution from the detector systems.  ...  The BER is < 5.90 · 10 −15 for serial data link speed of 1.25 Gbps and is < 3.65 · 10 −15 for serial data link speed of 1.90 Gbps, showing a good link quality of the M TR G serial data link.  ... 
doi:10.11588/heidok.00024727 fatcat:wleht7d4qfatfic2fslo2ikmdq

Example of a chip-FPGA communication

Byeong, Gyu Nam, Piljoo Choi, Hyun Kim, Ryang Ki, Dong Kim, Han-Ho Choi, Youn-Ho Jeon, Hyeon-Min Bae, Seongbin Kang, Yunsik Na, Munkyo Seo (+12 others)
2017 IDEC Journal of Integrated Circuits and Systems   unpublished
From FPGA On-chip T-line (5GHz Differential Clock) From chip to FPGA Fig. 3. The Architecture of the receiver. LA VCO Rx PR Tx PR FFE DEMUX MUX FPGA EQ Driver 10Gb/s Data In Receiver Fig. 4.  ...  A CDR logic and accumulator based on a Nyquist rate BBPD are used for phase lock and A FIFO transmits the parallel data to the transmitter in the IC.  ...  JTOL self-test is possible by implementing PRBS Generator, checker, and PRBS-based random generator in the FPGA. The implementation process is as follows.  ... 
fatcat:b32m4nyairacdd53k3zv73lary

A demonstrator system using a Xilinx ZYNQ FPGA and 6.6 Gbps optical links [article]

Ιωάννης Μπεστιντζάνος, University Of Ioannina
2021
The test is as follows: A PRBS sequence is generated on the transmitter, using the hard PRBS block of the MGTs and is then serialized and sent in the channel.  ...  Included is a PRBS (Pseudo -Random Binary Sequence) generator and checker block, which is very useful for debugging puproses.  ... 
doi:10.26268/heal.uoi.10892 fatcat:z3rspm4hxvbrvmtwq3n7do2lsi

Applications for Packetized Memory Interfaces

Myles Glen Watson
2015
Since current processors do not support packetized memory interfaces, a coherent processor bus is used as a memory interface for the DiskRAM project.  ...  Another source of overhead with high-speed serial links is the need to add methods for error detection, such as Cyclic Redundancy Code (CRC) calculations since the bit-error rate increases with bit rate  ...  Error Prevention and Detection As with any high-speed link, there is a non-negligible probability of bit errors.  ... 
doi:10.11588/heidok.00018228 fatcat:l2gvhf7nird5bp66qgjce44xhe

Erweiterung feldprogrammierbarer Bausteine um eine PCI Express Schnittstelle als Schlüsseltechnologie zur Vernetzung digitaler Systeme und künstlicher Intelligenz

Philipp Ledüc
2021
Der Entwicklungsansatz hat zum Ziel, FPGAs mit integriertem Serializer/Deserializer (SerDes) auf den Einsatz in hardwareübegreifenden Systemen der Künstlichen Intelligenz (KI) vorzubereiten.  ...  Allerdings versteht sich die Entwicklung als allgemeingültiger Ansatz, der auch anderen FPGA-Herstellern die Herangehensweise an die Thematik erleichtern und helfen soll, den notwendigen Entwicklungsaufwand  ...  rx_prbs_cnt_reset_i input 1 // RX PRBS Error counter reset reset the PRBS checker error counter rx_prbs_err_o output 1 // RX PRBS Error RX PRBS error detector: 0 no error detected 1 error  ... 
doi:10.26205/opus-3076 fatcat:biq3e7rq6zhmhknlo6helzmf7m

A 4D real-time tracking device for the LHCb Upgrade II [article]

MARCO PETRUZZO
2019
The setup of the gFEX board for the test of the MGT links is shown in Fig. 6 .4. In Link speed test with IBERT The BER test has been performed to confirm the quality of the links.  ...  Test with PRBS data A PRBS (pseudorandom binary sequence) is a sequence of 0 and 1 bits generated with a deterministic algorithm and represents a typical test pattern for evaluating the quality of serial  ... 
doi:10.13130/petruzzo-marco_phd2019-05-23 fatcat:u3y36srqkjb2jesa5am7xhpqua

Development and Characterisation of a Radiation Hard Readout Chip for the LHCb Outer Tracker Detector

Uwe Stange
2005
Several test chips and prototype versions of the TDC chip have been characterised. The present version of the chip OTIS1.2 fulfils all requirements and is ready for mass production.  ...  Zusammenfassung Entwicklung und Test eines strahlenharten Auslesechips für das äußere Spurkammersystem des LHCb-Detektors.  ...  Description Test chip for SRAM and DLL. The full featured memory prototype is an array of 186×240 cells with registered output plus supplementary input data generator and output data error checker.  ... 
doi:10.11588/heidok.00005908 fatcat:sq2747jp5fbubop7fagbvvdkai

Improvement of Power Quality of Distribution Network with DTC Drive Using UPQC

Ankush Malhar, Parag Nijhawan
2013 International Journal of Emerging Trends in Electrical and Electronics   unpublished
In this paper UPQC is realized using Simulink tool and it is tested for varying load condition and single line to ground fault.  ...  Unified Power Quality Conditioner (UPQC) is an active power filter which can compensate for both voltage and current at distribution level and controls the reactive power flow at the same time.  ...  I.INTRODUCTION There is an increasing demand for very high speed (high clock frequency) circuits.These high speed circuits will consume more power at clock distribution networks which should be reduced  ... 
fatcat:bnblzwx4yzc7hetwhs4bycaem4

ADAPTIVE 2011 Committee ADAPTIVE Advisory Chairs ADAPTIVE 2011 Technical Program Committee

Antonio Bucchiarone, Weirong Jiang, Serge Kernbach, Thomas Morris, Radu Calinescu, Thomas Morris, Serge Kernbach, Weirong Jiang, Sherif Abdelwahed, Habtamu Abie, José Calero, Hewlett-Packard Laboratories -Bristol (+56 others)
ADAPTIVE 2011 The Third International Conference on Adaptive and Self-Adaptive Systems and Applications   unpublished
Speed and scalability of changes require self-adaptation for special cases.  ...  We hope that ADAPTIVE 2011 was a successful international forum for the exchange of ideas and results between academia and industry and for the promotion of progress in the field of adaptive and self-adaptive  ...  ACKNOWLEDGEMENT The authors would like to thank Eric Lind for editorial help and our cooperating partners for sponsoring our project.  ... 
fatcat:z3xtmuwfjrdofca3k6lnoivgma