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An Array Allocation Scheme for Energy Reduction in Partitioned Memory Architectures [chapter]

K. Shyam, R. Govindarajan
Lecture Notes in Computer Science  
This paper presents a compiler technique that reduces the energy consumption of the memory subsystem, for an off-chip partitioned memory architecture having multiple memory banks and various lowpower operating  ...  More specifically, we propose an efficient array allocation scheme to reduce the number of simultaneously active memory banks, so that the other memory banks that are inactive can be put to low power modes  ...  Our heuristic approaches obtain, on an average, 20% reduction in memory subsystem energy over energy unaware array allocation methods, and 8% to 10% reduction over other competitive methods.  ... 
doi:10.1007/978-3-540-71229-9_3 dblp:conf/cc/ShyamG07 fatcat:h4niznuw7vcsziqy5fkgptlbwy

Energy-efficient address translation for virtual memory support in low-power and real-time embedded processors

Xiangrong Zhou, Peter Petrov
2005 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '05  
In this paper we present an application-driven address translation scheme for low-power and real-time embedded processors with virtual memory support.  ...  We outline an efficient compile-time algorithm for identifying these groups and allocate their translation entries optimally into the CTT.  ...  Figure 7 : 7 Hardware architecture Figure 9 : 9 Energy reductions of the proposed technique  ... 
doi:10.1145/1084834.1084848 dblp:conf/codes/ZhouP05 fatcat:qxp7sy7jufbtpogoklx5xmcuoe

Multi-level on-chip memory hierarchy design for embedded chip multiprocessors

O. Ozturk, M. Kandemir, M.J. Irwin, S. Tosun
2006 12th International Conference on Parallel and Distributed Systems - (ICPADS'06)  
This paper proposes an integer linear programming (ILP) solution to the combined problem of memory hierarchy design and data allocation in the context of embedded chip multiprocessors.  ...  The proposed solution uses compiler analysis to extract data access patterns of parallel processors and employs integer linear programming for determining optimal on-chip memory partitioning across processors  ...  Panda et al [11] present an elegant static data partitioning scheme for efficient utilization of scratch-pad memory.  ... 
doi:10.1109/icpads.2006.66 dblp:conf/icpads/OzturkKIT06 fatcat:7qq7ya35sve7nmwucjk7pcritu

Energy-Efficient Partitioning of Hybrid Caches in Multi-core Architecture [chapter]

Dongwoo Lee, Kiyoung Choi
2015 IFIP Advances in Information and Communication Technology  
DRAM Energy Consumption Area Overhead An area overhead of our technique comes from a partitioning scheme.  ...  This chapter proposes a technique that adopts the cache partitioning scheme in a hybrid cache for reducing the energy consumption.  ... 
doi:10.1007/978-3-319-25279-7_4 fatcat:pzs6ogqx55flde7bcz5xmf5eji

DR-SNUCA: An energy-scalable dynamically partitioned cache

Anshuman Gupta, Jack Sampson, Michael Bedford Taylor
2013 2013 IEEE 31st International Conference on Computer Design (ICCD)  
We propose a scalable dynamic cache-partitioning scheme, DR-SNUCA, which provides an energy-efficient way to reduce resource interference over caches shared among many processing elements.  ...  Our results show that DR-SNUCA reduces system energy consumption by 16.3% compared to associatively partitioned caches, such as DNUCA.  ...  Figure 5 shows that the greater energy-scalability of DR-SNUCA results in an average overall energy reduction of 16.3% compared to DNUCA.  ... 
doi:10.1109/iccd.2013.6657096 dblp:conf/iccd/GuptaST13 fatcat:fub4yqngjzfkdfzi4ngwra4444

Energy-efficient partitioning of hybrid caches in multi-core architecture

Dongwoo Lee, Kiyoung Choi
2014 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)  
This chapter presents a technique for reducing energy consumed by hybrid caches that have both SRAM and STT-RAM (Spin-Transfer Torque RAM) in multi-core architecture.  ...  Then a cache miss fills the corresponding block in the SRAM or STT-RAM region based on an existing technique called read-write aware region-based hybrid cache architecture.  ...  Cache Energy Consumption DRAM Energy Consumption Area Overhead An area overhead of our technique comes from a partitioning scheme.  ... 
doi:10.1109/vlsi-soc.2014.7004174 dblp:conf/vlsi/LeeC14 fatcat:6jp3mzleozbbvcdut4mws4dg54

Energy-oriented compiler optimizations for partitioned memory architectures

V. Delaluz, M. Kandemir, N. Vijaykrishnan, M. J. Irwin
2000 Proceedings of the international conference on Compilers, architectures, and synthesis for embedded systems - CASES '00  
This paper presents a compiler-based optimization framework that targets reducing the energy consumption in a partitioned off-chip memory architecture that contains multiple memory banks by organizing  ...  Our preliminary experiments show that the proposed framework improves memory energy by up to 86% over a scheme that keeps all the memory banks in the active (fully-operational) operating mode all the time  ...  We present a data placement (array allocation) algorithm that places the arrays used in an application across memory banks in an energy-conscious way to minimize the energy spent in the memory system.  ... 
doi:10.1145/354880.354900 dblp:conf/cases/DelaluzKVI00 fatcat:httjchxxnzhixeprmihjlyoc6y

EnVM

Pooja Roy, Manmohan Manoharan, Weng Fai Wong
2014 Proceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems - CASES '14  
Virtual memory is optimized for SRAM-based memory devices in which memory accesses are symmetric, i.e., the latency of read and write accesses are similar.  ...  The new virtual memory layout is implicitly used to allocate data to NVM and SRAM at any level of the memory hierarchy and is not dependant on the particular arrangements of the two partitions.  ...  Just as is the case for write reduction, EnVM is more energy efficient than SW1 and HW showing an average of 21% and 6% reduction in energy consumption, respectively.  ... 
doi:10.1145/2656106.2656121 dblp:conf/cases/RoyMW14 fatcat:rujkqfcs2jfelmah54j5publha

DRIM : A Low Power Dynamically Reconfigurable Instruction Memory Hierarchy for Embedded Systems

Zhiguo Ge, Weng-Fai Wong, Hock-Beng Lim
2007 2007 Design, Automation & Test in Europe Conference & Exhibition  
For a given hardware resource budget, an even better energy-performance may be achievable if the memory hierarchy can be reconfigured before each of these phases.  ...  In such systems, the instruction memory hierarchy consumes a large portion of the total energy consumption.  ...  Conclusion In this paper, we proposed a low power dynamically reconfigurable instruction memory hierarchy, called DRIM, for embedded systems.  ... 
doi:10.1109/date.2007.364484 fatcat:7nvtap7azzaz5g5zbl7j3ixxhy

Direct address translation for virtual memory in energy-efficient embedded systems

Xiangrong Zhou, Peter Petrov
2008 ACM Transactions on Embedded Computing Systems  
Direct address translation for virtual memory in energy-efficient embedded systems.  ...  This article presents a methodology for virtual memory support in energy-efficient embedded systems.  ...  This reduction of the tad and data arrays will offset the introduced SRAM array for the DTT and its leakage power.  ... 
doi:10.1145/1457246.1457251 fatcat:tcgxwkzpq5hr3dpxjfeus5lrre

Reconfigurable split data caches

Afrin Naz, Krishna Kavi, JungHwan Oh, Pierfrancesco Foglia
2007 Proceedings of the 2007 ACM symposium on Applied computing - SAC '07  
We use benchmark programs from the MiBench suite to show that our cache organization outperforms an 8k unified data cache in terms of miss rates, access times, energy consumption and silicon area.  ...  Our design enables the cache to be divided into multiple partitions that can be used for different processor activities other than conventional caching.  ...  By this we mean, if there is 75% reduction in area for our cache leading to a total L-1 size for scalar, victim and array portions, we allocate the same cache capacity for the unified data cache -thus  ... 
doi:10.1145/1244002.1244160 dblp:conf/sac/NazKOF07 fatcat:kkwrktmdwfd2fhe6fhman4vrty

Energy-efficient Java execution using local memory and object co-location

S. Kim, S. Tomar, N. Vijaykrishnan, M. Kandemir, M.J. Irwin
2004 IEE Proceedings - Computers and digital Techniques  
The object allocation strategy is implemented using an annotation-based approach and shown to be effective in improving performance and reducing the memory system energy consumption.  ...  This reduces the cache miss rate by up to 47%, and a subsequent reduction in the memory energy consumption by up to 49% is observed.  ...  [10] provides an annotation-based scheme for allocating arrays on the heap in order to reduce energy. Flin et al.  ... 
doi:10.1049/ip-cdt:20040186 fatcat:mdvcokpq65hzlferbvp42yyhk4

Compiler-managed partitioned data caches for low power

Rajiv Ravindran, Michael Chu, Scott Mahlke
2007 Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools - LCTES '07  
Using four direct-mapped partitions, we eliminated 25% of the tag checks and recorded an average 15% reduction in the energy-delay product compared to a hardware-managed 4-way set-associative cache.  ...  In comparison to traditional partitioning techniques, load and store instructions can individually specify the set of partitions for lookup and replacement.  ...  Zehra Sura of IBM TJ Watson Research Center for the initial discussions on partitioned caches.  ... 
doi:10.1145/1254766.1254809 dblp:conf/lctrts/RavindranCM07 fatcat:wavoh73t6ne27nusrbyznwdxz4

Compiler-managed partitioned data caches for low power

Rajiv Ravindran, Michael Chu, Scott Mahlke
2007 SIGPLAN notices  
Using four direct-mapped partitions, we eliminated 25% of the tag checks and recorded an average 15% reduction in the energy-delay product compared to a hardware-managed 4-way set-associative cache.  ...  In comparison to traditional partitioning techniques, load and store instructions can individually specify the set of partitions for lookup and replacement.  ...  Zehra Sura of IBM TJ Watson Research Center for the initial discussions on partitioned caches.  ... 
doi:10.1145/1273444.1254809 fatcat:icvlk2szozeaxlbqt4pmwrw77u

Data and memory optimization techniques for embedded systems

P. R. Panda, F. Catthoor, N. D. Dutt, K. Danckaert, E. Brockmeyer, C. Kulkarni, A. Vandercappelle, P. G. Kjeldsberg
2001 ACM Transactions on Design Automation of Electronic Systems  
We first examine architecture-independent optimizations in the form of code transformations.  ...  We next cover a broad spectrum of optimization techniques that address memory architectures at varying levels of granularity, ranging from register files to on-chip memory, data caches, and dynamic memory  ...  Allocating more or fewer memories has an effect on the chip area and on the energy consumption of the memory architecture (see Fig. 8 ).  ... 
doi:10.1145/375977.375978 fatcat:v7ekrrpchfc47nycvicmuouk2u
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