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Dynamic vectorization in the E2 dynamic multicore architecture

Andrew Putnam, Aaron Smith, Doug Burger
2011 SIGARCH Computer Architecture News  
Previous research has shown that Explicit Data Graph Execution (EDGE) instruction set architectures (ISA) allow for power efficient performance scaling.  ...  In this paper we describe the preliminary design of a new dynamic multicore processor called E2 that utilizes an EDGE ISA to allow for the dynamic composition of physical cores into logical processors.  ...  Figure 1 shows the basic architecture of an E2 processor containing 32 cores, and a block diagram of the internal structure of one physical core.  ... 
doi:10.1145/1926367.1926373 fatcat:7lj5z7tfzzawrpt63i4pvfguhi

ISAMAP: Instruction Mapping Driven by Dynamic Binary Translation [chapter]

Maxwell Souza, Daniel Nicácio, Guido Araújo
2011 Lecture Notes in Computer Science  
Dynamic Binary Translation (DBT) techniques have been largely used in the migration of legacy code and in the transparent execution of programs across different architectures.  ...  Our experimental results show that ISAMAP is capable of executing PowerPC code on an x86 host faster than the processor emulator QEMU, achieving speedups of up to 3.16x for SPEC CPU2000 programs.  ...  These descriptions, in assembly-like language, allows for an efficient mapping as it taps on the low-level machine code features of each architecture.  ... 
doi:10.1007/978-3-642-24322-6_11 fatcat:dxzyx2t625b3bn67fdkro7ky5a

A Conceptual Framework for Computer Architecture

S. S. Reddi, E. A. Feustel
1976 ACM Computing Surveys  
Architectures of some existing machines are considered and methods of associating architectural concepts with the components are established.  ...  The purpose of this paper is to describe the concepts, definitions, and ideas of computer architecture and to suggest that architecture can be viewed as composed of three components: physical organization  ...  The system hardware is designed to handle block structured languages and procedures efficiently by means of a stack mechanism and display registers.  ... 
doi:10.1145/356669.356673 fatcat:4q4ylloywfdlbkqi63km5ml5ba

Machine Code Optimization - Improving Executable Object Code [article]

Clinton F. Goss
2013 arXiv   pre-print
In addition to a theoretical treatment of this class of optimization techniques, this dissertation reports on an implementation of these techniques in a production environment.  ...  This dissertation explores classes of compiler optimization techniques that are applicable late in the compilation process, after all executable code for a program has been linked.  ...  Due to these results, I employ efficient heuristics to distribute the blocks.  ... 
arXiv:1308.4815v2 fatcat:zear5c63qrer5jfohashzdb4h4

Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs

Prabhat Mishra, Aviral Shrivastava, Nikil Dutt
2006 ACM Transactions on Design Automation of Electronic Systems  
Architecture description language (ADL)-Driven design space exploration and software toolkit generation strategies present a viable solution to this problem, providing a systematic mechanism for a top-down  ...  Furthermore, shrinking time-to-market demands, coupled with the need for product versioning through software modification of SOC platforms, have led to a significant increase in the software content of  ...  ACKNOWLEDGMENTS We would like to acknowledge the contributions of Professors Alex Nicolau, Mehrdad Reshadi, Ashok Halambi, Dr. Peter Grun, Dr. Partha Biswas, Dr.  ... 
doi:10.1145/1142980.1142985 fatcat:5zhydbvqs5huldhibt7nqa5qo4

An architecture of a dataflow single chip processor

S. Sakai, y. Yamaguchi, K. Hiraki, Y. Kodama, T. Yuba
1989 Proceedings of the 16th annual international symposium on Computer architecture - ISCA '89  
This paper focuses on an architecture of the EMC-R.  ...  pipeline and a register-based advanced control pipeline.  ...  Chief of the Computer Architecture Section for supporting this research, and the staff of the Computer Architecture Section for the fruitful discussions.  ... 
doi:10.1145/74925.74931 dblp:conf/isca/SakaiYHKY89 fatcat:yghqs4k3wfec3mwhnuvxgqjamu

An architecture of a dataflow single chip processor

S. Sakai, y. Yamaguchi, K. Hiraki, Y. Kodama, T. Yuba
1989 SIGARCH Computer Architecture News  
This paper focuses on an architecture of the EMC-R.  ...  pipeline and a register-based advanced control pipeline.  ...  Chief of the Computer Architecture Section for supporting this research, and the staff of the Computer Architecture Section for the fruitful discussions.  ... 
doi:10.1145/74926.74931 fatcat:w4anwfcudzfkzdsuq44yxmxeli

The case for virtual register machines

David Gregg, Andrew Beatty, Kevin Casey, Brian Davis, Andy Nisbet
2005 Science of Computer Programming  
A longrunning question in the design of virtual machines has been whether stack or register architectures can be implemented more efficiently with an interpreter.  ...  Many designers favour stack architectures since the location of operands is implicit in the stack pointer. In contrast, the operands of register machine instructions must be specified explicitly.  ...  The reviewers of IVME 03 made a similar contribution to an earlier version of this paper.  ... 
doi:10.1016/j.scico.2004.08.005 fatcat:w4wjgfwtnnefnax7zzm6foo5ca

The case for virtual register machines

Brian Davis, Andrew Beatty, Kevin Casey, David Gregg, John Waldron
2003 Proceedings of the 2003 workshop on Interpreters, Virtual Machines and Emulators - IVME '03  
A longrunning question in the design of virtual machines has been whether stack or register architectures can be implemented more efficiently with an interpreter.  ...  Many designers favour stack architectures since the location of operands is implicit in the stack pointer. In contrast, the operands of register machine instructions must be specified explicitly.  ...  The reviewers of IVME 03 made a similar contribution to an earlier version of this paper.  ... 
doi:10.1145/858570.858575 fatcat:aeui5zn445hdbdcxddsnnxodfi

XDSPCORE: a compiler-based configurable digital signal processor

A. Krall, I. Pryanishnikov, U. Hirnschrott, C. Panis
2004 IEEE Micro  
These constraints, along with a relatively narrow application domain, have led designers to create special architectural features, as found in the Harvard architecture, VLIW (very long instruction word  ...  The goal of this technology is to make DSP applications programmable entirely in a highlevel programming language like C, instead of assembly language.  ...  In the very large solution space provided by an architectural description language, very many core architectures are definable, but only a few are compatible with the development of an optimizing high-level  ... 
doi:10.1109/mm.2004.40 fatcat:lclck3wx2zd4zkilqn2oanqpdq

Beyond Dataflow

Borut Robi�, Jurij �ilc, Theo Ungerer
2000 Journal of Computing and Information Technology  
, and the need to associatively match pending operations with available functional units.  ...  This paper presents some recent advanced dataflow architectures.  ...  Instructions with matching tokens are executed. Instructions can emit tokens or write to register file. In 1993, an upgrade to EM-4, called EM-X, was developed (Kodama et al., 1995) .  ... 
doi:10.2498/cit.2000.02.01 fatcat:3bonvcsg6jbnzj3uouzwkc5tcm

A preliminary architecture for a basic data-flow processor

Jack B. Dennis, David P. Misunas
1998 25 years of the international symposia on Computer architecture (selected papers) - ISCA '98  
The architecture offers an unusual solution to the problem of structuring and managing a two-level memory system.  ...  A processor is described which can achieve highly parallel execution of programs represented in dataflow form.  ...  Registers specified to act as operand registers change state with the arrival of packets directed to them.  ... 
doi:10.1145/285930.286058 dblp:conf/isca/DennisM98 fatcat:2ssuln6iofbzxm2qvylbl6tsxi

A preliminary architecture for a basic data-flow processor

Jack B. Dennis, David P. Misunas
1975 Proceedings of the 2nd annual symposium on Computer architecture - ISCA '75  
The architecture offers an unusual solution to the problem of structuring and managing a two-level memory system.  ...  A processor is described which can achieve highly parallel execution of programs represented in dataflow form.  ...  Registers specified to act as operand registers change state with the arrival of packets directed to them.  ... 
doi:10.1145/642089.642111 dblp:conf/isca/DennisM74 fatcat:dd7o2bp77jfsjlcvfcunjtu7sa

Embedded software in real-time signal processing systems: design technologies

G. Goossens, J. Van Praet, D. Lanneer, W. Geurts, A. Kifli, C. Liem, P.G. Paulin
1997 Proceedings of the IEEE  
Moreover, due to the shorter lifetimes and the architectural specialization of many processor cores, processor designers are often compelled to neglect the issue of compiler support.  ...  One of the key requirements is more efficient software compilation technology.  ...  DSP and ASIP architectures often have a strongly heterogeneous register structure with many special-purpose registers.  ... 
doi:10.1109/5.558718 fatcat:jtn2aeo4ybcwfgc67rdsdqjhei

A preliminary architecture for a basic data-flow processor

Jack B. Dennis, David P. Misunas
1974 SIGARCH Computer Architecture News  
The architecture offers an unusual solution to the problem of structuring and managing a two-level memory system.  ...  A processor is described which can achieve highly parallel execution of programs represented in dataflow form.  ...  Registers specified to act as operand registers change state with the arrival of packets directed to them.  ... 
doi:10.1145/641675.642111 fatcat:qqftnmzmkjh3zcv7vsx7wdqjzy
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